Concurrent hardware/software development
By M. Buckley
Embedded System Engineering
www.esemagazine.co.uk
Matt Buckley describes a methodology to give software developers access to working emulations of IP blocks generated from the system specification – allowing software and hardware development to proceed concurrently.
Many designers recognise the need to concurrently develop system software and hardware. There are many tools now available that allow a system architect to specify a system design independent of the hardware/software division. However, before implementation can begin a division between the hardware and the software must be specified. At this point the development of software and hardware generally follow separate paths. The hardware and software designers will both be given a copy of the system specification created by the system architect. The hardware and software are then developed independently from each other. The hardware designers verify their design via simulation with test benches that they develop based on the system specification. Similarly the software designers use the system specification to create an abstract model of the hardware system. This abstract model is then used to develop the software design.
Read more ...
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- USB Host IP-Core Hardware and Software Concurrent Development
- Concurrent hardware/software development
- Virtual Prototyping Environment for Multi-core SoC Hardware and Software Development
- Improving Software Driver Development and Hardware Verification Productivity using Virtual Platforms
Latest Articles
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks