Choosing a Processor for Machine Learning at the Edge
By Manisha Agrawal, Texas Instruments
EETimes (June 23, 2019)
Not all machine learning models need processing on the order of several TOPS. Understanding the performance, latency and accuracy need of your application is a critical first step to choose a processor for machine learning at the edge.
Machine learning has become popular for solving machine vision and other embedded computing problems. While classical machine learning algorithms need human intervention to extract features from data, machine learning algorithms or network models learn how to extract important features in data and make intelligent predictions about that data.
Below, figure 1 shows a few examples where machine learning technology is adding intelligence to a variety of devices. In smart home appliances like a smart oven, machine learning can be used to classify food inside the oven and set the cooking temperature and time of the oven accordingly. In factories, machine learning can be used for detecting defects in the products or it can be used for predictive maintenance to help predict the remaining useful life of the motor or detecting anomaly in motor operations. In a vehicle, it can be used to detect cars, pedestrians, traffic signs, etc. on the road. It can also be used in devices doing natural language translation.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- A novel 3D buffer memory for AI and machine learning
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- MIPI in next generation of AI IoT devices at the edge
- A Survey on SoC Security Verification Methods at the Pre-silicon Stage
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS