Using drowsy cores to lower power in multicore SoCs
Cody Croxton, Ben Eckermann and David Lapp
EETimes (6/29/2011 2:18 PM EDT)
Freescale engineers describe a cascading power management technique that steers tasks to a smaller number of cores during non-peak activity periods so that the idle cores can enter a minimal-power or “drowsy” state. Multicore processing has enabled higher and higher levels of processing capability, but with a price: higher levels of power consumption. Cascading power management is a technique that steers tasks to a smaller number of cores during non-peak activity periods so that the idle cores can enter a minimal-power or “drowsy” state.
When packet traffic increases again, the technique allows a rapid return to fully loaded conditions. Cascading power management is not simply a power-saving technique; it is also a workload management technique that distributes packet processing in a more efficient way.
To read the full article, click here
Related Semiconductor IP
- DeWarp IP
- 6-bit, 12 GSPS Flash ADC - GlobalFoundries 22nm
- LunaNet AFS LDPC Encoder and Decoder IP Core
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
Related Articles
- How NoCs ace power management and functional safety in SoCs
- Get the right mix when integrating Power Management Solutions into SoCs
- Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs
- Multicore microprocessors and embedded multicore SOCs have very different needs
Latest Articles
- VolTune: A Fine-Grained Runtime Voltage Control Architecture for FPGA Systems
- A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
- Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
- SoK: From Silicon to Netlist and Beyond Two Decades of Hardware Reverse Engineering Research
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks