Blistering traffic speeds: a detailed look inside PCI Express
Steve Kolokowsky and Trevor Davis, Cypress Semiconductor
Oct 24, 2005 (10:48 PM)
CommsDesign
PCI Express is an implementation of the PCI computer bus that uses existing PCI programming concepts and communications standards, based on a much faster serial communications system. In fact, PCI Express is a scalable bus that provides as little as 250Mbytes/second at a 2.5Ghz signaling rate up to 8Gbytes/second in the first spec revision. Higher bandwidths can be achieved by increasing clock speed or bus width.
This technology, like many other bus protocols, uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry information from a transmitting component to a receiving component (See Figure 1). As transmitted packets flow through each layer, they are modified to contain additional information necessary to handle packets at those layers
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- How HyperTransport and PCI Express complement each other
- Advanced switching boosts PCI Express
- Compatibility issue slows PCI Express
- With StarFabric as an on-ramp, the PCI Express Advanced Switching is ready
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design