Automatic C-to-VHDL testbench generation shortens FPGA development time
Sunil Sahoo (Aldec) and Brian Durwood (Impulse)
EETimes (4/11/2012 12:05 PM EDT)
Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad use of FPGA-embedded processor cores, has resulted in the increased use of FPGAs for complex, algorithmic processing logic as well as the traditional uses of glue and control logic. The use of FPGAs for complex processing can create an overall design that may combine C, VHDL and Verilog. This creates a challenge when it comes to verification, and a particular challenge to the new generation of FPGA users who are migrating over from software development to hardware acceleration.
New design C-based methods and new testbench generators enable developers to mix C and HDL. In this extended tool flow, the core application is developed in C. First level verification is performed in software simulation using Visual Studio or a comparable tool. After this functionality-only test, the developer selects a target FPGA or a target FPGA-enabled board and then verifies functionality at that level, either in-system or using a hardware simulator. The latter method saves time by reducing the iterations through FPGA place-and-route. A key productivity boost in this case is that the test files for the VHDL simulator are generated from the original C design files. There is no disconnect from design engineering to design for test.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- USB 20Gbps Device Controller
- SM4 Cipher Engine
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
Related White Papers
- eTBc: A Semi-Automatic Testbench Generation Tool
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- Retargeting IP -> Effective designs eye next generation
- Retargeting IP -> ASIC generation revamped for IP reuse
Latest White Papers
- Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
- eFPGA – Hidden Engine of Tomorrow’s High-Frequency Trading Systems
- aTENNuate: Optimized Real-time Speech Enhancement with Deep SSMs on RawAudio
- Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference
- Hardware Acceleration of Kolmogorov-Arnold Network (KAN) in Large-Scale Systems