Infusing Speed and Visibility Into ASIC Verification

High-performance, high-capacity FPGAs continue to experience an exponential growth in usage, both in their role as prototypes for ASIC/SoC designs and as systems in their own right. These designs typically involve complex combinations of hardware and embedded software (and also, possibly, application software).

This is resulting in a verification crisis because detecting, isolating, debugging, and correcting bugs now consumes significantly more time, money, and engineering resources than creating the design in the first place.

The problem is that bugs in this class of design can be buried deep in the system and can manifest themselves in non-deterministic ways based on complex and unexpected interactions between the hardware and the software. Simply detecting these bugs can require extremely long and time-consuming test sequences.

Once a problem is detected, actually debugging the design requires a significant amount of time and effort. Furthermore, when verification tests are performed using real-world data, such as a live video stream from a digital camera, an intermittent bug may be difficult, if not impossible, to replicate.

There are a variety of verification options available to engineers, including software simulation, hardware simulation acceleration, hardware emulation, and FPGA-based prototypes. Each approach has its advantages and disadvantages (Table 1 below).

RTL simulators, for example, are relatively inexpensive, but full-system verification performed using this approach is extremely slow. One major advantage of software simulation is visibility into the design. Having said this, as more signals are monitored and the values of these signals are captured, simulation slows even farther.

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