An introduction to offloading CPUs to FPGAs - Hardware programming for software developers
Grzegorz Gancarczyk, Maciej Wielgosz, and Kazimierz Wiatr
EETimes (3/7/2013 12:07 PM EST)
Several factors are disrupting the traditional monopoly of microprocessors for being the chip of choice for C algorithms. These include the cost and accessibility of cross-compilation tools, the power and speed limitations of microprocessors, and the availability of more reliable building blocks.
In this article, three university researchers break down the problem into understandable steps that the average developer can follow to determine if FPGAs are worth the (decreasing) bother and – if the answer is "yes" – how to go about it. This is based on hundreds of hours of class and lab testing. The authors are willing to share teaching materials, curricula, and advice with any certified university. If there is sufficient interest in this article, they will produce two follow-on articles going into more details with regard to lab work and cycle-accurate incremental improvement.
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- Time Sensitive Networking: An Introduction to TSN
- An Introduction to Post-Quantum Cryptography Algorithms
- An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
- Introduction to Low Dropout (LDO) Linear Voltage Regulators
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY