A bridging model for ESL synthesis

 
SystemC has recently become popular for electronic system-level (ESL) modeling because of the growing complexity of systems on a chip (SoCs), and because of the ubiquity of C and C++. It facilitates the incorporation of embedded software, instruction set simulators and cycle-accurate simulators, which are usually written in C or C++. Transaction-level modeling (TLM) not only provides a higher level of abstraction, but also faster simulation speed.

Unfortunately, hardware-accurate modeling and synthesis to hardware are problematic in SystemC and, with its current approach, are likely to remain so. The root cause is the model of computation — threads and events.

First, as eloquently argued by Lee and Ousterhout (in [L1] and [01]), the thread model is very difficult to use for any serious concurrent programming, and hardware systems have complex concurrency. Second, threads and events are so far removed from hardware that hardware-accuracy is difficult, and synthesis intractable, unless the design is written essentially as RTL. Behavioral synthesis is often cited as a solution, but its current incarnation only works for applications with loop-and-array scientific/technical algorithms, and leaves untouched the majority of hardware blocks, which have heterogeneous and irregular structures with complex control.

What ESL needs is a bridging model of hardware, rather than threads and events. A bridging model raises the level of abstraction while retaining the fundamental essence of hardware: fine-grain parallel state transitions on fixed circuit structures organized into a module hierarchy. This will allow architects and designers to work at a high level while retaining a sense of predictability and control in the structures they design. An implementation of such a bridging model exists in Bluespec SystemVerilog (BSV) — and, the recently introduced ESL Synthesis Extensions (ESE) to SystemC address this need for SystemC.

To read the full article, click here