When Developing New Silicon IP, Is First Pass Success Possible?
Brandt Braswell, Distinguished Member of the Technical Staff, Freescale Semiconductor
Planet Analog (3/31/2015)
If you have worked in the semiconductor industry for more than a few years I am sure you have heard senior leadership speak about the need for your integrated circuit designs to be first pass successes and not the typical two to three spins or more to reach the targeted performance. The question is this: Is first pass success feasible and should be expected? I do not want to stir up a hornets nest with my response but the answer to the question is that it depends. Depends on what you say? Well, the answer depends on several different interwoven complexities that can determine if first pass success is possible. I would like to explore some possible ways to answer this question. Furthermore, the complexity of this question increases when developing complex mixed signal IC’s.
For IC development on the sub nanometer technologies it becomes very expensive to not get it right the first time or at least close to being right the first time. In the end, many project business decisions count on the design development as production ready by pass two or the business case may not work. As we move forward down the integration technology curve and more of the embedded system type solutions become standard practice, the idea of a first pass success in the nanometer technologies become even more important to meeting the needs of the business. In addition, the turn time from concept to final customer integration is shortening as well. Customers are expecting quicker turn times of the development of silicon – even if it is full custom- as their customers are demanding faster innovation to remain competitive. Therefore, the need to find a path to first pass success is important for the success of the project.
So what are some of the decision criteria if followed would help enable your designs to be first pass successes?
To read the full article, click here
Related Semiconductor IP
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
- PUF Hardware Premium with key wrap and certification support
Related White Papers
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- SoC silicon is first-time success following simulation and validation of novel array processor
- Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success
- Careful IP Integration Key to First-Pass Silicon
Latest White Papers
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
- Data Movement Is the Energy Bottleneck of Today’s SoCs