Validating your GNU platform toolchain: tips and techniques
Mark Mitchell and Anil Khanna, Mentor Graphics
EETimes (9/30/2011 8:04 PM EDT)
Open-source tools for your open-source Android/Linux platform.
In the past few years we've seen the embedded design community move away from proprietary software development tools and move decisively closer to open-source software (OSS) development.
As one would expect, accompanying this shift is an increased demand for proven, top-quality OSS tools. For embedded systems developers designing for embedded Linux, the GNU toolchain is the most popular choice due to its standing as the natural toolchain of the Linux kernel community.*
So how do you obtain a GNU toolchain? You can opt to purchase a commercial toolchain from an established vendor or you may decide to build the toolchain yourself. Successfully building a GNU toolchain, while a significant achievement, is only half the work. Meaningfully testing and validating to ensure the production-worthiness of your toolchain, is the critical second half.
With its massive codebase of 10 million lines or more, adequately testing the GNU toolchain can pose a mammoth task, as illustrated by Table 1. It's vital to create a methodical validation strategy to achieve maximal testing of the various components.
To read the full article, click here
Related Semiconductor IP
- Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
- PUF FPGA-Xilinx Premium with key wrap
- ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- ASIL-B Ready PUF Hardware Base
- PUF Software Premium with key wrap and certification support
Related White Papers
- Pondering the SoC platform
- Panel finds many ways to build a platform
- Platform approach speeds MIPS-based SoCs
- Platform IP for all seasons
Latest White Papers
- Boosting RISC-V SoC performance for AI and ML applications
- e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
- How to design secure SoCs, Part II: Key Management
- Seven Key Advantages of Implementing eFPGA with Soft IP vs. Hard IP
- Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU