Tools get incomplete grade for analog IP creation

Tools get incomplete grade for analog IP creation
By Stephan Ohr, EE Times
June 21, 2001 (7:14 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010621S0075

LAS VEGAS — The scarcity of analog designers and the increasing need to place analog cells into system-on-chip designs are creating a demand for EDA tools that facilitate the creation and integration of analog intellectual property, according to semiconductor manufacturers and EDA tool vendors on a Wednesday (June 20) panel at the Design Automation Conference. Both users and vendors said that a new generation of tools that allows digital designers to create and incorporate analog IP into their design flows is three-to-five years from development and maturity.

This tentative convergence of semiconductor makers' and tool makers' wish lists stands in marked contrast to tensions that surfaced at DAC panels in years past. This year's debate, entitled "When will the analog design flow catch up with digital methodology?" pitted a “red team” of providers against a “blue team” of users, with few apparent sparks. The blue team included manufacturers STMi croelectronics, Taiwan Semiconductor Manufacturing Co. Ltd., and Matsushita Electric Corp.; the red team included Neolinear Corp., Barcelona Design and Cadence Design Systems Inc.

For example, there was a decided overlap between the compliments extended by Akira Matsuzawa, general manager of Matsushita's Semiconductor Components Group (Osaka, Japan), and the projections made for analog synthesis by Mar Hershenson, founder and chief executive officer of Barcelona Design (Sunnyvale, Calif.). Matsuzawa, a former analog designer, said analog synthesis tools have demonstrated the ability to automate the process of turning analog schematics into a buildable floor plan, but still require a reliable design methodology and behavioral model builder. These issues could be resolved in a three- to five-year time frame, he said.

The methodology, though largely for digital design, is already in place, said Hershenson. But unlike digital top-down design flows, the "handoff" between behavioral modeling in Verilog a nd structural modeling and manipulation in Spice, for example, is incomplete, she said. And foundry and process dependencies mean there are few reusable, customizable analog IP blocks, she said. An analog expert is typically needed to complete the repeated iterations of selecting a topology, sizing it for a new process, and developing the means for testing it. Currently missing is a easy way to generate a wide variety of analog IP blocks, a fully-stocked library of analog functions, and a robust synthesis engine to make use of this library, Hershenson said. Even so, a fully functional library and engine — now easily accessible to digital designers — could easily be in place within three-to-five years, she said.

On the customers' blue team, Andrew Moore, North American business development manager for TSMC, seemed to agree that analog synthesis tools could play a key role in generating new IP and completing time-to-market goals. Moore agreed that a library of analog-like functions was indeed c oming together, and was making a substantial contribution to the speed with which a new design could tape out.

But on the issue of design quality, Moore appeared to break ranks. Substrate analyzers were the most promising mixed-signal tools, he said. And analog IP for a wide variety of functions will soon be available from a wide variety of sources, he suggested. The task will be to make the IP work properly on a digital SoC, he said. Many of these properties, for example, will require wide isolation rings and guard bands to keep the noise they generate from penetrating other parts of a circuit. Such guard bands are not economical to manufacture. "When you cram everything together to make a $5 Bluetooth part, all bets are off," he said.

Phillipe Magarshack, senior design manager with STMicroelectronics, never challenged the conjecture of what could be achieved in three-to-five years. Rather, he emphasized the current trend toward implementing analog functions in vanilla CMOS and utilizing multiple f abrication facilities to build them. His company was interested in mechanisms for rapidly generating analog IP and migrating it to new processes, Magarshack said.

He identified three types of IP functions: One he called "commodity IP," by which he meant standard linear functions such as op amps, phase-locked loops, A/D converters and D/A converters. For these, IP synthesis tools must perform transistor sizing and automatic layout. A second type of IP, called "star IP," involves precision analog expertise in such functions as LNAs and precision op amps. For these, synthesis tools must control the design flow from process characterization to behavioral modeling to manufacturing yield analysis, Magarshack said. The third type of IP, called "process migration," requires automatic resizing tools. For these, analog synthesis tools are "promising . . . but not production ready,” Magarshack said.

Ron Rohrer, the Carnegie Mellon University professor who now serves as chairman of Neolinear, objected to the la st point. Neolinear's tools are specifically intended for resizing and process migration problems. Today it is possible to develop entire cell layouts for voltage controlled oscillators and charge pumps from otherwise unsized schematics, according to Rohrer. This differs sharply from Rohrer's position in 1967, when he wrote a paper stating the impossibility of synthesizing anything, given the unavailability of adequate computer power. Evaluating one transistor at that time would have required three days using an IBM mainframe, Rohrer said at the time.

A synthesized cell on a piece of analog IP uses less area and less power than a hand-crafted, "guru-driven" layout, Rohrer said.