Tips for doing effective hardware/firmware codesign: Part 2
By Gary Stringham, Gary Stringham & Associates, LLC
Embedded.com (September 17, 2013)
A success factor of embedded systems products is its performance. Is it fast enough to meet the customer’s requirements and expectations? But is it cheap enough that the customer will buy it? Putting a V-8 engine on a lawn mower will definitely provide sufficient performance; however, it will be too expensive for the consumer. Performance must be weighed against cost.
Previously discussed in Part 1 were tradeoffs between polling a status bit and waiting for an interrupt. Interrupts allow firmware to work on something else until the event occurs, and then be notified immediately when it does occur.
But judicious use of interrupts is required to avoid bogging down the system with interrupts occurring too frequently. Likewise, other aspects of the hardware/firmware interaction require judicious designs to ensure optimal performance.
This section discusses a few techniques to maximize the performance at the hardware/firmware interface without incurring too much cost in the platform.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- Tips for doing effective hardware/firmware codesign
- Basics of hardware/firmware interface codesign
- Optimizing Analog Layouts: Techniques for Effective Layout Matching
- Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity