Think Big for Ultra-Low Power IoT SoCs
Kurt Shuler, VP Marketing, Arteris
EETimes (8/4/2016 09:42 AM EDT)
Some of the best ideas in creating breakthrough IoT innovation could be gleaned from the design of much larger SoCs.
The so-called Internet of Things is rife with design challenges.
Many SoC engineers in this field are trying to cram the greatest possible processing power within the lowest possible power budget.
That’s what it’s going to take to provide value at the network edge as more and more devices deploy sensors, microcontrollers and modems to send information back to the core for big data analytics. Or so the conventional wisdom goes.
But that could be a mistake.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- Save power in IoT SoCs by leveraging ADC characteristics
- Novel and efficient power grid design for lesser metal layer process SOC's
- Define Analog Sensor Interfaces In IoT SoCs
- Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs
Latest White Papers
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity
- Memory Prefetching Evaluation of Scientific Applications on a Modern HPC Arm-Based Processor