Think Big for Ultra-Low Power IoT SoCs
Kurt Shuler, VP Marketing, Arteris
EETimes (8/4/2016 09:42 AM EDT)
Some of the best ideas in creating breakthrough IoT innovation could be gleaned from the design of much larger SoCs.
The so-called Internet of Things is rife with design challenges.
Many SoC engineers in this field are trying to cram the greatest possible processing power within the lowest possible power budget.
That’s what it’s going to take to provide value at the network edge as more and more devices deploy sensors, microcontrollers and modems to send information back to the core for big data analytics. Or so the conventional wisdom goes.
But that could be a mistake.
To read the full article, click here
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
- 0.9V/2.5V I/O Library in TSMC 55nm
- 1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
Related White Papers
- Save power in IoT SoCs by leveraging ADC characteristics
- A RISC-V ISA Extension For Ultra-Low Power IoT Wireless Signal Processing
- Novel and efficient power grid design for lesser metal layer process SOC's
- Define Analog Sensor Interfaces In IoT SoCs
Latest White Papers
- What tamper detection IP brings to SoC designs
- Analyzing Modern NVIDIA GPU cores
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
- Leveraging RISC-V as a Unified, Heterogeneous Platform for Next-Gen AI Chips
- Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core