The ''nuts and bolts'' of Integrating PCI Express into your design

In this paper, we discuss how to integrate a full PCI Express (PCIe) solution into your chip design. The paper summarizes types of integration, IP selection, lab set up, integration timelines, and any future migration of the design.

Types of integration
There are three levels of production that you can design for – low-, medium-, and high-volume. Field programmable gate arrays (FPGAs) are typically best suited for prototypes and low-volume production, either with an internal PHY or with a recommended external third-party PHY. Start-up costs of FPGA are very low, and parts can be purchased in single quantities. However, there are integration issues with FPGAs, and the path to volume production can be complex.

If medium- to high-volume is expected, development can still take place using an FPGA, with a migration to an Application Specific Standard Product (ASSP) PCIe bridge or Structured ASIC. With a bridge chip, the end result will have surplus silicon, but the bridge chip is also the easiest solution for achieving volume production. If a chip has all the functionality and performance you need, simply buy it off the shelf. (It is beyond the scope of this paper to describe ASSP PCIe bridges or endpoints)

Another medium- to high-volume solution is a Structured ASIC. Structured ASICs provide the exact functionality and performance you need, without sacrificing development time or introducing design risk. Structured ASICs also provide a completely seamless path from prototype to production.

For solutions where high-volume production is expected from the outset, Standard Cell ASIC solutions are best. The upfront risk is much higher and time-to-market is much longer, but after the chip is in production, costs are lowest.

To read the full article, click here