The common silicon issues in analog IP integration

By Kedar Patankar, P2F Semi
Planet Analog (April 24, 2021)

Despite the fears of the last decade that Moore’s Law had finally reached its end, the microelectronics sector has continued to adapt to new physical constraints and product requirements through sustained innovation and creativity. A major portion of that creative energy has gone into the development of analog, RF and mixed-signal blocks as embeddable IP.

The selection of analog/RF/mixed-signal IP now available is both broad and deep. One can find a multitude of hardware blocks in 7 nm (and in some cases even 5 nm) in the following major categories:

1. PLL and DLL: offered in a wide range of speed, jitter and power specifications
2. DAC and ADC: available with resolutions of 8-bit to 24-bit and up to 300 MSPS
3. PHYs and SerDes: targeted at a broad selection of markets such as wireless (Wi-Fi and 5G), networking (LAN, WAN and Storage), computing (USB, PCIe, MIPI) and memories (DDR, including G and LP variants, as well as HBM and many others)
4. Smaller components that can be assembled to create personalized analog front-ends (AFEs), power management functions, and RF modules

The industry has produced a steady stream of process technology advancements to support the never-ending demand for higher gate counts, lower power, greater performance and increased functionality. That includes triple well isolation, silicon-on-insulator, P+ guard rings, FinFET and trench isolation. Many of these features contributed to the proliferation of analog, RF, and mixed-signal IP we see today. These substrate additions also reduced the magnitude of some of the complications with which designers have been contending in ultra-deep submicron—problems such as analog noise sources hidden in slew rates, impedance matching and termination complications, and circuits that support tremendous bandwidths.

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