Structured ASICs take FPGA prototypes into volume production

(09/13/2004 9:17 AM EDT)
   

Over the last few years, FPGAs have come to play an increasingly important role in the development methodology of ASICs. Programmable logic offers designers an ideal way to quickly develop prototype circuits. Its programmable flexibility and minimal NRE costs make it an excellent platform for experimenting with and verifying a design.

While they serve as excellent tools for prototyping, FPGAs are usually far too expensive for high-volume, production applications. Moreover, they frequently cannot meet a design's requirements for speed and power consumption.

To overcome those limitations, designers often opt to convert to standard-cell ASICs when their designs hit production volumes. However, some inherent limitations in the FPGA architecture can complicate the conversion. For example, most FPGAs use lookup table-based logic that tends to be area-inefficient and has a one-to-one ratio of lookup tables (LUTs) to registers. This can be particularly problematic for designs that are register-intensive.

Second, memories in an FPGA are comprised of small blocks with configurable rows and columns. This architectural component makes it difficult for designers to efficiently create larger blocks of memory. Third, fixed (column/row/diagonal) routing resources in an FPGA can affect placement and, more important, impede performance. Pre-defined clock trees feed all registers in an FPGA.

To accelerate the FPGA design process, most vendors now offer third-party developed IP blocks, such as high-speed I/Os or embedded processors. But designers using those blocks face expensive licensing costs when they migrate their design to an ASIC. Furthermore, dedicated IP, such as multipliers, adders and MACs, is often proprietary in nature and must be modified to meet the requirements of the ASIC manufacturer's process.

Simplified migration

Structured ASICs, a new class of silicon platform, lower the traditionally high NRE costs of standard cell-based ASICs by preconfiguring some of the device's logic, memory and I/O. They offer a number of advantages over standard-cell ASICs in the migration process.

Basic logic in a structured ASIC is comprised of a sea of modules. While modules vary from vendor to vendor, in general they all feature some combination of muxes, NANDs and inverters and therefore simplify the process of mapping FPGA logic into a denser and more efficient architecture.

Structured-ASIC vendors offer a variety of memory block sizes that often match FPGAs in the number of total bits and configurability. The variety of available block sizes can simplify the implementation of larger memory structures. However, designers must carefully choose the number of blocks of each size they will use in their design since they must incur the cost for any unused memory blocks.

Routing within a structured ASIC is not fixed and is created on a need-only basis. This capability allows designers to create the most efficient routes. Unlike FPGAs, for example, structured ASICs do not have any hanging junction capacitance. They also optimize clock trees, by placing flip-flops in a manner that minimizes the clock tree net to improve speed and reduce power.

One of the biggest challenges engineers face in any design migration is pin compatibility. Structured-ASIC vendors such as ChipX have addressed this need by offering extremely flexible I/Os that cover a wide array of standards, much as the I/Os in FPGAs do.

The test process in an FPGA is fairly expensive and time-consuming since all the circuitry in the device must be tested. By migrating their design to a structured ASIC, designers can reduce their test cost since the preconfigured sections of the device are already proven in silicon.

While structured ASICs offer a number of important advantages in the FPGA-to-ASIC migration process, designers must still deal with significant challenges. For example, in some instances designers employ FPGAs fabricated in a smaller silicon process technology than the structured ASIC in an attempt to approach the performance and power consumption requirements of a design. That discrepancy can result in voltage compatibility problems.

Second, one of the most costly and time-consuming issues designers still face in the migration design process is the re-qualification of IP. The ASIC development flow is distinctly different from the FPGA design process. More often than not, proprietary IP used in the development of an FPGA must be modified and requalified for use in a structured-ASIC design. This process remains an issue with the use of structured ASICs and standard-cell ASICs since it can consume design resources and extend the development cycle.

The programmability and rapid turnaround capabilities inherent in the FPGA architecture continue to make it an excellent tool for prototyping a silicon design. But the same attributes that provide an advantage in the prototype stage can pose significant obstacles in the transformation of a chip design to a lower-cost, standard-cell ASIC platform.

While FPGA and ASIC vendors have dramatically simplified the migration process over the past several years, issues such as memory size, routing efficiency, pin compatibility and testing remain. By providing a highly flexible and configurable architecture, structured ASICs can help designers circumvent many of these problems and still preserve the performance, power and cost benefits associated with a standard-cell ASIC.

Gokul Krishnan is product-marketing manager and Suhail Zain is product architect at ChipX (Santa Clara, Calif.).

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