Shifting Mindsets: Static Verification Transforms SoC Design at RT Level

Pranav Ashar, CTO, Real Intent Inc.
EETimes (3/6/2015 08:29 AM EST)

Teams 'shift left' to tackle challenges earlier in the design flow, says CTO of Real Intent, an EDA software design tools company.

We are at the dawn of a new age of digital verification for SoCs. A fundamental change is underway. We are moving away from a tool and technology approach — “I have a hammer, where are some nails?” — and toward a verification-objective mindset for design sign-off, such as “Does my design achieve reset in two cycles?”

Objective-driven verification at the RT level now is being accomplished using static-verification technologies. Static verification comprises deep semantic analysis (DSA) and formal methods. DSA is about understanding the purpose and intent of logic, flip-flops, state machines, etc. in a design, in the context of the verification objective being addressed. When this understanding is at the core of an EDA tool set, a major part of the sign-off process happens before the use or need of formal analysis.

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