SOC isn't cutting it yet. Is multi-chip package a better answer today?

To date, "those who have chosen SOC have . . . come up with costlier solutions," contends Clark Fuhs, senior analyst at Dataquest in San Jose. "SOC adds complexity," he points out. "At 0.25 microns, the premium was low enough for a decent return, but costs rise below 0.20 microns. Since many SOCs are application-specific," he notes, "short-run devices cost more" and price themselves out of contention.

"At the beginning of 1999 we were enthusiastic about SOC," comments Sal Mastroianni, vice president at Motorola Semiconductor's DigitalDNA Laboratories in Tucson, Ariz. But now, he says, "we realize SOC isn't always appropriate [so we] follow two approaches, SOC and SIP [system-in-package, a multi-chip solution]."

An IBM Microelectronics researcher is pushing hard now for system-on-package (SOP), or SIP, because he maintains that it's a superior alternative to SOCs in an increasing number of designs. Edmund Sprogis, senior engineer in IBM C orp.'s Advanced Technology Division, points to the emergence of Asian-made memory products that use wire bonding to merge flash and SRAM die. He calls this the tip of the iceberg for SOP. "The floodgates are opening with these flash/SRAM products, so why not attempt this style of design more broadly?"

SOP is superior to SOC in a number of ways, Sprogis claims. Both the silicon and tests for system-chip designs typically are more costly and slower [getting] to market than their system-on-package cousins, he says.

SOC designs also usually have lower yields and do not efficiently use the process technology in which the final chip is made. "If you are not using the finest geometry of the patterning technology you have available across the entire die, then you are throwing capability away. That's just inherently inefficient," the IBM engineer says. SOP designs provide a better way to leverage the capabilities of different process technologies in a single device.

For now at least, it has become clea r to many designers that SOC is not suitable for many applications, and that other approaches often can outperform the it, such as multi-chip solutions in off-the-shelf packaging or multi-chip modules (MCM).

"For [wireless communication] needs, SOC solutions aren't available," declares Loren Anderson, senior marketing and product manager at Omnipoint Technologies Inc. in Colorado Springs, Colo.

Another naysayer is Mark Levi, analog division marketing director at National Semiconductor Corp. in Santa Clara, Calif. "It's often better to segregate analog and digital functions. They can be housed in single packages--or CSPs," he notes. "Analog functions take little area, so the CSP approach isn't painful. If you need a single package, you don't even need MCMs; off-the-shelf BGAs work too."

Others point out the current limitations of SOC design tools. "Designers are used to dealing with smaller devices and tools appropriate to less integration," says Dave Francis, partner at Integrated Interconnect ion Intelligence Inc. in Montara, Calif. "SOCs also have high IP content, and making cores cooperate is difficult," he adds. "Physical interfacing and process compatibility issues all make SOC design time consuming."

For many, the higher costs associated with SOCs are the main problem. Higher "mask costs are an issue," declares Robert Castellano, president, Information Network Inc., a New Tripoli, Pa., market researcher. "Each critical-layer 0.18-micron mask costs $35,000-to-$40,000 vs. $5,000-to-$6,000 at 0.35 microns," he says. "We estimate that a 0.1-micron critical-layer mask set will cost $100,000, with a [full] set for a 25-layer IC [costing] $2.5 million."

What this means is an SOC will need a long production run to amortize costs and generate returns. Short-run SOCs aren't practical, designers say. And the economics indicate that many SOCs would be more viable as multi-chip designs, with the package or printed circuit boards supplying the "metallization."

"Multi-chip solutions are alwa ys attractive," according to consultant Francis. "The elements are proven, design-and-debug is fast, you get to market faster, and you're cost effective in smaller volumes."

Nor is package size a drawback, he adds. "Packaging is transparent to the OEM. The ultimate package may be a BGA, though it may house two to six chips. We can even use lead-frame packages for two- or three-chip solutions."

If you need a "system solution" today, you have three choices, according to Dataquest's Fuhs.

The first is go to next-generation lithography at 193 or 157 nanometers. But "in practice, these technologies aren't ready," he points out.

Second, he says, "design your way out by adding programmable logic and configuring an SOC for multiple applications. You increase production and spread costs over more sockets. This isn't easy," he warns, "though some companies succeed with it." Final choice would be to go to multiple chips in a single package, "off-the-shelf packages like BGAs," Fuhs says. "The chips a nd packages are cheap, reliable, and available--saving time and cost."

Fuhs predicts all three approaches will co-exist. "Use SOCs where you need quantity, want to minimize cost through batch processing, or need maximum performance with minimum size or pin count." If size and performance are moderate factors, he says that the programmable SOC will be less expensive. "When you must reach market fast with a low-cost, reliable product, and area is not an issue, multi-chip solutions win," he figures.

And that's the way the business is going right now. SOC proponents such as Integrated Device Technology, LSI Logic, Lucent, Motorola, and Texas Instruments all offer multi-chip solutions as well.

It's the economics that decides now between SOC or SIP, says Motorola's Mastroianni. For example, SIP comes out on top in major markets such as wireless and portable systems because it offers faster turnaround and lower cost. They are critical factors in these markets.

With SOC, The economics become less attractive with SOC, because yields suffer with each additional function and mask. Many SOCs require embedded RAM and that can add several mask layers and process steps, Mastroianni. "Each [one] adds cost and reduces yield."

Maintaining high yields is critical. For example, the additional masking for non-volatile RAM could cut yield by 10%, he says. SOC mask costs are higher since runs tend to be short and mask costs are higher below 0.20 micron, he adds.

Integrated Device Technology Inc., which offers both SOC and SIP, turns out most of its system-level products in multi-chip packages, says Philip Bourekas, vice president for strategic marketing at the Santa Clara, Calif., company. "SOC and SIP are appropriate at different points in a product's lifetime," he says.

Take cable modems, for example. "The first-generation units had to be multi-chip because there were no standards," Bourekas says. "Flexibility was the key to reaching market. After things settle down, cost becomes the driver, and SOC makes sense."

But to some experts, it's only a matter of time before SOCs take over. Richard Kerslake, system-level integration business manager at Texas Instruments Inc. in Dallas, views multi-chip solutions only as stopgaps. "Every time multi-chip solutions surface, integrated approaches body-check them."

Right now, though, he says that "multi-package solutions are becoming attractive with CSP because you [can] pack lots of functionality into a little area, [which] makes testing easier and reduces rework. You get to market fast," he adds.

As for the higher cost of masks with SOCs, Kerslake says that "mask cost disappears as a factor when you think of video games or set-top boxes with millions of units. OEMs want SOCs for maximum integration and minimum cost."

"SOC is our default approach but we aren't religious about this," declares Mark Pinto, semiconductor business unit manager at Lucent Technologies Inc. in Allentown, Pa. "We put as much on one chip as possible and use multi-chip for incompatible functions, or as backup strategies."

"SOC makes sense," he says, "where the device can be pure CMOS--including functions like IF or RF, and RAM,--and so long as chip-size and performance requirements are appropriate."

But some functions are difficult, if not impossible, to integrate, Pinto notes. "Optoelectronics, for example, demands gallium arsenide rather than Silicon. And you can integrate flash, but it's costly. What you need for a successful SOC," he says, "is vanilla CMOS."

One class of product that rarely will be integrated, Pinto says, is power. Because these devices dissipate a lot of heat, SOC packaging grows bulky and expensive, offsetting SOC's cost and size advantages, he notes.

Lucent designs programmable logic in SOCs. One example is a V.90 packet radio SOC for GSM. This chip includes a DSP, microprocessor, flash, SRAM, A-to-D conversion, embedded debugging, as well as analog func tions. But the heart of the design is 120,000 programmable gates where the OEM can store his own bit stream, tailoring the SOC to specific applications. Lucent also offers FPGAs in SOCs.

LSI Logic Inc. makes no bones about being a big SOC booster. "We specialize in SOC," declares Ronnie Vassishta, director of ASIC technology marketing at the San Jose chip maker. "We've sold SOCs into CDMA and GSM phones, DVD players, digital cameras, computers, and set-top boxes. LSI also is now offering SOCs with FPGA in 50,000 gate blocks."

Mixed-signal functions figure in many of these designs, and while Vassishta admits that noise can be a problem, he says that LSI uses such features as guard bands and place-and-route to overcome it. And when the supply voltage limits either output or the signal-to-noise ratio, LSI embeds power conditioning circuitry in the SOC to increase voltage swing, he adds.

As far as Vassishta is concerned, LSI Logic customers nearly always want SOC now because it allows more integra tion and lower life-cycle cost. This shift will continue, he insists. But even LSI Logic offers multi-chip CSP technology as an option. --Additional reporting by Rick Merritt of EE Times