Satellite modems structure Internet access

Satellite modems structure Internet access
By Mark Vanderaar and Richard Price, EE Times
November 21, 2003 (1:58 p.m. EST)
URL: http://www.eetimes.com/story/OEG20031121S0039

Structured ASICs are a new class of devices that deal with the burgeoning costs of developing traditional ASICs and the time taken to obtain the first fully functional devices. Efficient Channel Coding Inc. (ECC) turned to those ASICs, from Altera Corp., in the IPX-5100, a modem designed for broadband Internet access through satellites. The IPX-5100 interfaces with conventional geostationary satellites as well as the iPSTAR-1 satellite, providing broadband access rates up to 8 Mbits/second download and 4 Mbits/s upload.

The IPX-5100 uses ECC's Adaptive Coding and Modulation technology to dynamically change the channel coding and modulation technique on the fly according to the time-varying channel conditions. These methods dramatically improve the satellite system's capacity by customizing the link to an individual IPX-5100, allowing optimized use of the limited satellite bandwidth.

Initially the IPX-5100 modem was designed with an FPGA to prot otype and verify the functionality of the Adaptive Coding and Modulation technology. Using the prototype, ECC was able to field trial and qualify the modem addressing the iPSTARTM system requirements. The next step was to move to a lower cost solution once field qualifications were approved and the terminal was ready for medium-volume production.

There are merits to considering at the start what devices to use beyond the prototyping phase. An ASIC or a conversion ASIC (an ASIC derived through conversion of an FPGA netlist) requires synthesis or resynthesis of the design, generating a netlist different from the one used to prototype. This difference adds risk and could increase costs as well as impair market-entry plans for the product should the first silicon not function. It would be nice to have a path to seamlessly migrate the prototype-proven netlist to a device suitable for high-volume production.

ECC evaluated various structured ASICs and conversion ASICs, but found that only Altera's HardCopy devices supported such a requirement. The migration of the design from prototype to medium-volume production was aided by pin compatibility between FPGA and the HardCopy device. Choosing the right I/O and package not only helped ECC to replace the FPGA with the HardCopy part, but also vastly eased the requalification of the IPX-5100 modem.

ECC used a combination of Altera and third-party software to prototype the design, perform physical synthesis and static timing analysis and generate the design database to transfer to Altera for migration to the structured ASIC. Having an integrated design environment that supports synthesis and simulation tools allowed ECC to leverage its existing tool suite and take the design from prototype to silicon as fast as possible.

Coding to synchronous design principles facilitated several design steps, including synthesis, timing analysis and testability of the device. While it is always enticing to get that extra megahertz through a code segment that violates these e stablished rules, inadvertent usage can considerably hamper verification and testability. ECC used vendor tools to examine the design for such violations. This helped to ensure that the design could be migrated smoothly in the quickest possible time and, eventually, aided manufacturing test.

HardCopy devices use typical ASIC design back-end flows to translate a signed-off netlist to layout. Some of the key events in the migration process that Altera performed to ensure that the layout stayed close to the design in functionality and performance were clock tree synthesis, parasitic extraction, back-annotated static timing analysis and formal verification.

Timing is of particular interest in converting from a programmable to a fixed device. HardCopy devices have an inherent speed advantage of up to 63 per cent over their FPGA counterparts. Of course, this is due to the absence of programmability, but also to shorter interconnect lengths stemming from a smaller die size. But this does not make timing an alysis of the HardCopy device unnecessary. Any timing violations discovered during back-annotated static timing analysis were fixed with proper buffer insertions and routing constraints.

In many cases, an application can benefit from the faster hard devices. In this particular design, timing analysis indicated that the HardCopy part could meet performance specifications for the modem that the FPGA prototype had not met. So it was possible to improve the performance of the system during the transition. Once ECC signed off on the final timing, the database was taped-out for manufacture.

In other ways, the changes to the design were minimized. SRAM-based FPGAs require a configuration device that programs the FPGA on power-on. However, once the design has stabilized, the programmability is unnecessary (hence, so is the configuration device). HardCopy devices provide configuration emulation features that not only enabled ECC to retain the existing board and architecture but also avoided any need to change the software.

The design was checked by ECC and Altera's design engineers to see if it violated industry-standard design-for-testability techniques. The embedded test logic such as scan, memory built-in self test and JTAG structures provided vehicles to test the manufactured device. Further, ECC did not provide any functional vectors to Altera as the design used structural testing through ATPG vectors.

HardCopy ASICs are manufactured as base arrays up to a certain process step ahead of specific designs. Once the database was ready, design information was routed on the “parked” wafers using the top three metal layers. Packaged and tested samples were available in less than sevens. When ECC replaced the FPGA on the board with the HardCopy device, the IPX-5100 worked flawlessly, meeting the system requirements. The seamless migration of the prototype-proven design delivered fully functional first silicon, enabling the IPX-5100's quick entry in the marketplace with minimum development costs.

Mar k Vanderaar is chief executive officer at Efficient Channel Coding Inc. (Brooklyn Heights, Ohio) and Richard Price is senior manager, HardCopy Design Center, at Altera Corp. (San Jose, Calif.).

See related chart