How to raise the RTL abstraction level and design conciseness with SystemVerilog - Part 1

With the advent of advanced HDLs – such as SystemVerilog – that provide new and powerful language constructs, current hardware modeling styles can now be enhanced both in terms of abstraction level and overall efficiency.

Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs. This paper will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs.

The following four steps are proposed to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach for Verilog designers to gradually migrate to SystemVerilog:

   1. Enhance conciseness and expressiveness of designs.
   2. Add built-in checks to avoid design issues.
   3. Design efficient FSM and RAM/ROM memory models.
   4. Graduate to object oriented generic hardware designs.

Part 1 of this article will examine Steps1 and 2 – conciseness of expression and built-in code verification. Adopting these first two steps can contribute to descriptiveness of the design and correlation of the RTL and gate-level netlist.

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