Reuse eases wireless SoC efforts

Putting together system blocks or intellectual property will require multiple sources both for the IP developer and for the tools used to develop the IP. Designers will have to deal with different blocks in wireless applications.

The RF components in the design may be the core expertise of the system integrator and require analog tools for modeling the continuous time effects. The baseband signal is the information riding on the RF carrier; its decoding algorithms may be licensed from a semiconductor house. These algorithms, much like those for speech decoding, are typically modeled using data flow descriptions. For the control logic, the IP design teams may have used finite-state-machine descriptions and the software protocol stack may be licensed from a source using specification-description -language tools. And all these elements must work together with the application software defining central parts of the product features, the all-important functionality that will attract consumers.

Together with the increasing complexity of SoC designs, such challenges cause design teams to adopt advanced design methodologies such as integration platform-based design. In addition, the design abstraction at which trade-off decisions and hand-off in the design chain occur is changing.

The complexity of the designs combined with time-to-market pressure means it is unfeasible to start every new design from scratch. Even soft IP reuse (with modification) is difficult to apply, because every change in the IP requires a complete and sufficient set of verification scenarios to be run again. Instead, design teams now use IP reuse techniques where no modifications to the reused blocks are made, a method learned from printed-circuit-board design. This leads to platform-based design techniques in w hich the basic architectural platform is maintained through a product generation. Products are differentiated in two ways: in software or by adding hardware components from the platform library using standard interfaces. This enables automatic communication synthesis to fit in the additional blocks.

A platform-based design methodology changes the way design teams work together, even across company borders in the design supply chain. In this process, abstraction takes an increasingly important role. It is no longer acceptable for a semiconductor company to provide just an implementation model of the platform. Abstracted system platform models are required to allow the system integrator to assess trade-offs and derivative design considerations early in the design cycle. Moreover, they provide a consistent API to software developers for configuring and modifying the platform provided by their suppliers.

In this context, consider two integration challenges in wireless designs: the interacti on between RF and baseband decoders, and the interfaces between baseband and speech decoders with control-dominated hardware.

RF circuitry typically distorts the baseband signal somewhat. While co-simulating these effects using analog simulation combined with RTL baseband models is technically possible, it is not practical. The simulation time would not allow enough test data to be run to assess the trade-offs efficiently.

Efficient interface

One solution is through the combination of Cadence's SpectreRF and Signal Processing Worksystem (SPW), which provides a link using K models and J models that represent only the distortion of the baseband signal and abstract the analog continuous-time characteristics into sampled, characterized models. Using abstraction, these models do not invoke the analog simulator when executing together with SPW C++-based models. This link provides an efficient interface between the analog, continuous-time simulation paradigm and the data-flow simulation used in DSP.

Once the baseband signal is decoded, it will be forwarded to control-dominated system blocks. These might decide about further processing needs such as speech or video processing or simple data storage. Based on the Open Modeling Interface standard (OMI; IEEE 1499), such a link between data-flow and control blocks is available between Cadence's SPW for DSP design and the Virtual Component Codesign (VCC) for system-level intellectual-property integration.

Control models can be simulated efficiently using the discrete-event computational model. A characteristic of these models is that they execute in simulation once any of the inputs are available. By comparison, the central characteristic of a data-flow model is that the model is executed once all the inputs for the computation are available. In data-flow simulation, a significant speed increase is gained over standard discrete-event simulation.

When an OMI-compliant SPW model is imported into VCC, the importation generates the necessary logic to execute the imported data-flow model in a discrete-event environment. For this purpose a trigger module is automatically inserted; in simulation, it activates the module once all its inputs are available. Similar links through OMI exist for specification-description-language modeling tools. These enable the assessment of integration aspects of software protocol stacks with the hardware/software environment.

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