Meeting signal integrity requirements in FPGAs with high-end memory interfaces

    
Wider parallel data buses, increasing data rates, and multiple loads are challenges for high-end memory interface designers. The demand for higher bandwidth and throughput is driving the requirement for even faster clock frequencies. As valid signal windows shrink, signal integrity (SI) becomes a dominant factor in ensuring that memory interfaces perform flawlessly.

Chip and PCB-level design techniques can improve Simultaneous Switching Output (SSO) characteristics, making it easier to achieve the signal integrity required in wider memory interfaces. EDA vendors are making a wide range of tools available to designers for optimizing the signal integrity quality of memory interfaces. Features that are integrated on the FPGA silicon die, such as Digitally Controlled Impedance (DCI), simplify the PCB layout design and enhance performance. This article discusses these design techniques and hardware experiment results, illustrating the effect of design parameters on signal integrity.

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