Making your UWB solutions ''Future Proof''

 
New technologies bring with them new opportunities as well as new uncertainties. In order to make best use of technology, one has to be prepared for today as well as for the future. This often involves tradeoffs between current opportunities and future potential. In this article, the effort is to illustrate a possible tradeoff one has to make while developing the solutions based on Ultra Wideband.

The challenge: Optimal vs. Flexible

WiMedia Common Radio Platform provides the firm foundation for the implementation of different flavors of UWB solutions such as Wireless USB, Internet Protocol (IP) over UWB (WiNET), Bluetooth over UWB and Wireless 1394. Among these, Certified Wireless USB (CWUSB) is likely to be the first “killer application” for Ultra Wideband as the USB-IF (Implementers Forum) has launched the product certifications for Wireless USB based products. Other technologies such as Bluetooth over UWB and IP over UWB (WiNET) will soon become available when the standardization completes and product certification programs are launched. Because of the unique proposition of the Common Radio Platform (supporting multiple PALs) a designer faces the challenge of designing a solution which is optimal for the current applications today, yet flexible enough to adapt to the newer applications and technologies as they evolve over time.  

Different Technologies, Different Requirements

WiMedia Common Radio Platform provides the architecture to adopt different technologies such as Certified Wireless USB, WiNET and Bluetooth over UWB over the WiMedia MAC and PHY.  

 
Figure 1: WiMedia Common Radio Platform

From this figure one may imply a layering approach where entire WiMedia MAC is common across all solutions and an “adaptation layer” is developed on top to address different applications such as Wireless USB, WiNET and Bluetooth over UWB. If one were to take the “layered approach” for the implementation, entire WiMedia MAC functionality needs to be fully implemented. But this layered approach may not result in an optimal design.

Let’s take the example of Certified Wireless USB - CWUSB specification defines a Wireless USB channel which consists of Micro-scheduled Management Commands which define how the wireless USB packets are transmitted within the DRP reservations done by the Wireless USB host. The micro-schedules have a granularity smaller than the Media Access Slots (MAS) defined in the WiMedia MAC specification. The micro-scheduling functionality can not be implemented efficiently if CWUSB is treated as a “layer above the MAC”. Moreover, all the WiMedia MAC features may not be needed for all product personalities addressed by CWUSB (see table below).  As a result, it may be common to implement only those features of WiMedia MAC and CWUSB spec which are needed for a given product personality as one single layer. Given the fact that Wireless USB may enable newer applications which were earlier not envisaged with wired USB, it may be prudent to design a solution which can support all product personalities such as Wireless USB device, Wireless USB host and a Dual Role Device with incremental efforts. Similarly, the applications over UWB technology (such as Bluetooth over UWB and IP over UWB) are still evolving. The challenge would be to have an architecture which can address different product personalities without significant design change.    

One typical approach to provide flexibility to adapt to evolving applications is to implement most of the functionality in software. Such a solution may be very demanding on the embedded CPUs typically used in the solutions such as CUWSB device. Moreover, it may not be scalable for higher throughput. A better approach would be to have an optimal partitioning of the entire WiMedia MAC functionality into hardware and software. The design should be modular so that the optimal solution can be developed by scaling up or scaling down the basic architecture for the given product personality.  

Another design consideration for addressing the various product personalities would be optimal performance. The performance includes throughput, silicon area of the ASIC and power consumption. The objective of the design should be to address different product personalities optimally without making changes to the design which adds schedule risks. For example, the design should be capable of scaling down to low power and low area by scaling down buffer space and core clock while keeping the design logic unchanged. Similarly, higher throughputs should be achievable by adding more buffers and/or scaling up the core clock without changing the logic design.

The above approach should allow one to reduce the time to market for various applications (current or future) and yet be optimal enough given the constraints.

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