It Takes tools to Raise a Programmable Mixed Signal SOC

Modern systems-on-chip are very complex devices that place large demands on the skills of the developer. This complexity forces the SoC vendor to supply tools to manage the design process for all of the functional elements, as well as the verification steps needed to put these elements together into a complete system-level design.

The challenge in this development process becomes even tougher when the SoC in question has programmable analog and digital blocks that can take on many different functions. If one of these analog blocks can become the basis for either a switched-capacitor filter or an analog-to-digital converter, very different strategies for tools, design and verification need to be used to ensure the success of the design. The broader the range of system-level functions that can be supported by a device, the more the tool set used must integrate traditional system-level tools and methodologies.

Microcontroller units (MCUs) were originally developed to be single-chip computers with all the necessary circuitry to interface to the outside world. As the embedded applications using these devices become more complex, additional circuitry that's external to the MCU is required. This is especially true for analog-intensive applications, as these usually require many external analog components — somewhat defeating the original goal of creating a single-chip solution.

The programmable system-on-chip mixed-signal array with on-chip controller was conceived to replace MCUs, as well as this extra analog and digital circuitry, and deliver true SoC capability. The PSoC accomplishes this by providing the user with blocks of analog and digital logic that can be configured to handle the same functions that typically require external circuitry on traditional MCUs. The development tool set for the PSoC, called PSoC Designer, integrates many of the system-level design tasks that once took place at the board level. With the PSoC, many of those tasks can now be implemented at the chip level.

An example of this is using the PSoC to implement a power line modem. The basic function of the PLM is to transmit information over the same conductors that are used to power a device. The functions of filtering, modulation and correlation are all accomplished using the on-chip analog blocks. The development tool set provides assistance with configuring each of these separate functions, optimizing that function to the needs of this particular application and integrating these discrete functions into the PLM.

A PLM reference design has been made that transmits and receives signals at 131.850 and 133.050 kHz that are encoded on top of the 60-Hz, 110-volt ac power. The modem receiver has a four-pole band-pass filter to reject out-of-band noise and a modulator to shift the received signal to an intermediate frequency. The IF signal drives a correlator whose output is low-pass-filtered, then detected with a comparator to provide a digital signal to a UART.

The input band-pass is a switched-capacitor filter designed using a filter design "wizard," which is integrated as part of PSoC Designer. Given the center frequency, bandwidth and gain, the user can optimize analog block capacitor values and clock frequency to meet performance requirements and clocking constraints. The wizard automatically makes the correct register settings to implement the desired filter.

The modulator uses a polarity-toggling switch, driven by the internally generated local oscillator, on the input leg of a band-pass filter. The IF filter is a two- pole band-pass filter, which is designed using the same filter wizard.

The correlator works by multiplying the IF signal by a delayed replica of itself, so that the output at one input frequency is maximum positive and at the other input frequency is maximum negative. The delay is executed with two digital blocks working as a shift register delay line. The multiplication is implemented with another modulator, where the polarity toggling switch is on the input leg of a low-pass filter. The design of the delay system is a trade-off of output voltage difference at the two frequencies, response time, digital delay block count and clock synchronization and is implemented with either a spreadsheet or a Matlab script.

The low-pass filter on the correlator output PSoC is also designed with the filter wizard. As a result of available capacitor ratios and clocking synchronization constraints, the on-chip filter is not at a low enough corner frequency to adequately reject all of the sampling aliases, so an additional active low-pass filter is implemented using external passive components and a programmable-gain amplifier block. This filter is designed using the spreadsheet provided in an online application note. The PGA output drives a hysteresis comparator and finally the UART, resulting in 10-millivolt sensitivity for reliable 1,200-baud communication.

Powerful tools are required to implement modern SoCs, and this is especially true for programmable SoCs. The PSoC Designer tool set allows the user to create complex applications like the PLM, and has system-level capabilities and wizards to make the design and verification process go quickly. It really does take a village of tools to raise a programmable mixed-signal SoC.

Dennis Seguine (seg@cypress.com) is senior applications manager and Nathan John (nwj@cypress.com) is director of strategic marketing at Cypress MicroSystems (Lynwood, Wash.), a subsidiary of Cypress Semiconductor Corp.

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