Integration brings CPU into analog design

Integration brings CPU into analog design
By Ron Wilson, EE Times
January 21, 2003 (3:55 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030121S0041

SUNNYVALE, Calif. — A small, specialized analog design house may face the challenge of integration with fear and trembling. But when a market you depend on starts moving to higher levels of integration, you have two choices: integrate along with it or become an intellectual-property (IP) vendor.

The Kendin Operation of Micrel Semiconductor (Sunnyvale, Calif.) faced just that situation. Kendin started out about seven years ago as one of a small number of vendors doing high-performance mixed-signal chips in standard CMOS logic processes. That expertise led them into the 10/100 Ethernet transceiver business, which they pursued up the integration ladder from standalone transceivers to five-port MAC/PHY devices.

But the integration demands continued to rise, leading Kendin, which along the way had been acquired by Micrel, to integrate a switch onto the chip. With the cost of Ethernet switch boxes plummeting to the level of countertop kitchen app liances, the integration had to continue.

Recently, the company faced the need to integrate a substantial CPU onto the five-port transceiver/switch device. The CPU would bring protocol-handling capabilities onto the die, potentially eliminating an expensive external chip from the switch boxes.

ARM-9 gets nod

After some reflection and pencil-on-paper work, the design team decided to go for an ARM-9 CPU. That would provide enough horsepower for the baseline protocol tasks. Pencil and paper also suggested, however, that offloading some of the more cycle-hungry tasks to an external accelerator — mainly a checksum engine — and a beefed-up direct memory access (DMA) controller would free a lot of headroom that customers could use for added features. In the end that proved to be the case, with at least one customer implementing a SoHo-class firewall in the ARM-9.

Chip design was not simply a matter of moving hard IP from previous chips and gluing on a CPU core, said Kendin vice pre sident of engineering Jung-Chen Lin. “We tore our five-port switch apart and repartitioned it for this design as two separate sets of blocks.'' Changes were dictated by the bus architecture imposed by the ARM 9, the DMA-centric data flow approach and the need for local FIFOs to maximize throughput.

Rather than constructing an executable system model to determine appropriate FIFO sizes, the team — always watching the budget — relied on experience with previous designs to gauge sizing. Similarly, the design of the protocol engine was derived from studies the company had already conducted for a Gbit-switch project.

Physical design was handled by an outside contractor working with isolation constraints developed by the analog designers at Kendin. Once again, experience dictated the design. Lin believes that there are no adequate models available, even in the mature 0.18-micron process they used, for all of the possible coupling mechanisms that could affect the sensitive transceivers. The analog designers increased the level of isolation used in previous designs, in particular permitting no over-routing of the analog cores and taking careful measures to prevent supply coupling. They found, to their relief, no degradation in analog performance on the new chip relative to the previous design.

In that way, the Kendin team did the floor planning for the chip, the digital RTL design and the analog design while the contractor did the final place and route. Kendin did the design rule checks. During chip-level verification the analog blocks — which were independently verified using a combination of Spice and Spectre by the analog team — were replaced with behavioral models in Verilog, which were then combined with the digital design Verilog to form a full-chip model.

Verification was done with the testbench from the five-port MAC/PHY part.

Now in production, the chip came out working. More interestingly, it met the performance expectations of the design team.

At 166 MHz the chip a chieves 93-Mbit/second throughput — significantly higher than most ARM-based designs and near the level of a competitive product based on the much more powerful SH-4 CPU. By substituting experience for expensive system-level modeling tools, and by staying with a conservative process, a small team on a limited budget was able to achieve first-time success. It is a useful example for lean times.