How to Integrate Flash Device Programming and Reduce Costs
(08/17/2005 3:16 PM EDT), EE Times
In the late 1980s memory devices changed in a flash. Intel and Toshiba spearheaded the development of flash process technology to create a new class of products. Prior to flash-based memory devices, designers used electrically programmable read-only memories (EPROMs) or electrically erasable programmable read-only memory (EEPROMs) for non-volatile storage of digital information; both posed major challenges.
EPROMs offered high-densities and were reliable, but could only be erased by exposing the silicon to strong ultraviolet (UV) light. Early EPROMs were packaged with a transparent glass window on the top for this purpose. The glass window significantly added to the cost of the devices so later versions were built with an opaque top, making these devices non-erasable after programming. Engineers lost flexibility to change or update their designs once the memory devices, then known as one-time programmable (OTP) EPROMs, were programmed. Manufacturers also had to account for fallout from programming failures.
The advent of EEPROMs solved the erase problem. Instead of exposing silicon to strong UV light, EEPROMs are programmed and erased by applying high voltage (12V to 20V) to certain device pins. For low-voltage devices, however, a spike in power consumption during programming and erase potentially causes system vulnerabilities. Similar to EPROMs, EEPROMs also require long write and erase times since devices can only be written-to or erased one byte at a time. EEPROMs also have higher costs since each device cell requires a separate read, write and erase circuit, adding to the overall die size.
Flash-based EEPROMs, introduced in 1988, was an answer for engineers looking for high-density, low-cost memory devices that were easy to program and erase. Flash memory devices can be electrically erased in blocks instead of bytes without the need for irregularly high voltages, considerably reducing erase times. This block-based erase method allows the device to share erase circuits within a block, reducing both die size and costs. Densities for flash memory devices have increased exponentially since their introduction, with vendors offering as much as eight gigabytes of storage capacity.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related White Papers
- How to reduce board management costs, failures, and design time
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
- How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it
- Basics of SRAM PUF and how to deploy it for IoT security
Latest White Papers
- New Realities Demand a New Approach to System Verification and Validation
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Sustainable Hardware Specialization
- PCIe IP With Enhanced Security For The Automotive Market
- Top 5 Reasons why CPU is the Best Processor for AI Inference