How to reduce board management costs, failures, and design time
Shyam Chandra, Lattice Semiconductor
EETimes (10/12/2010 8:40 AM EDT)
In order to meet the demands of increased functionality, performance, and reduced power, many modern circuit boards use highly integrated CPUs, ASSPs, ASICs, and memory devices to implement the circuit board’s main function (the payload function).
Boards of this complexity are particularly common in equipment designed for communications infrastructures, computer servers, and higher end industrial and medical systems. Because the ICs on the board are usually fabricated with fine transistor geometries, they require multiple power supply rails with tight tolerances to operate. Typically, seven to ten supplies are needed in a complex circuit board, with higher numbers not unusual.
The management of these supplies – along with other system management tasks – is increasing in complexity and cost. This is leading many board designers to ask: "How can I reduce the cost and complexity associated with implementing board management?"
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related White Papers
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
- How to design secure SoCs, Part II: Key Management
- Tools For Reprogrammability -> Programmable ASICs to reduce costs
- How to Integrate Flash Device Programming and Reduce Costs
Latest White Papers
- How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
- Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
- Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
- How Mature-Technology ASICs Can Give You the Edge
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY