How to reduce board management costs, failures, and design time
Shyam Chandra, Lattice Semiconductor
EETimes (10/12/2010 8:40 AM EDT)
In order to meet the demands of increased functionality, performance, and reduced power, many modern circuit boards use highly integrated CPUs, ASSPs, ASICs, and memory devices to implement the circuit board’s main function (the payload function).
Boards of this complexity are particularly common in equipment designed for communications infrastructures, computer servers, and higher end industrial and medical systems. Because the ICs on the board are usually fabricated with fine transistor geometries, they require multiple power supply rails with tight tolerances to operate. Typically, seven to ten supplies are needed in a complex circuit board, with higher numbers not unusual.
The management of these supplies – along with other system management tasks – is increasing in complexity and cost. This is leading many board designers to ask: "How can I reduce the cost and complexity associated with implementing board management?"
To read the full article, click here
Related Semiconductor IP
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- FH-OFDM Modem
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- PQC CRYSTALS core for accelerating NIST FIPS 202 FIPS 203 and FIPS 204
- USB Full Speed Transceiver
Related White Papers
- How to Reduce FPGA Logic Cell Usage by >x5 for Floating-Point FFTs
- How to design secure SoCs, Part II: Key Management
- Tools For Reprogrammability -> Programmable ASICs to reduce costs
- How to Integrate Flash Device Programming and Reduce Costs
Latest White Papers
- FastPath: A Hybrid Approach for Efficient Hardware Security Verification
- Automotive IP-Cores: Evolution and Future Perspectives
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models