How to design FPGA-based advanced PCI Express endpoint solutions

With plans in place to increase bandwidth to 5 Gbps in Generation 2 and 10 Gbps in Generation 3, the PCIe bus is expected to be the dominant high-bandwidth interconnect for several years to come. (For more information on the PCIe specification or compliance information, visit www.PCISIG.com.)

With scaleable lane widths from ×1 to ×32 lanes and advanced features such as traffic classes, virtual channels, hot-plug, and power management, the PCIe interface provides support for a wide range of applications – ranging from a simple upgrade from PCI to an ×1 PCIe endpoint device to advanced high-bandwidth ×8 PCIe communications endpoint devices.

Fig 1 shows the topology of a sample PCIe system. The CPU is connected to a root device and is responsible for configuring and enumerating all plug-and-play PCI Express endpoint devices in a system. Because the PCIe system is point-to-point, switch devices are necessary to grow the number of devices or endpoints in a system. A switch has one "upward-facing" port and numerous "downward-facing" ports. These downward facing ports connect to the working devices or endpoints of a system.

1. PCI Express system topology.

Although only one root exists in any system, there are one or more endpoint devices. For example, a standard PC motherboard provides three to seven expansion PCIe slots. The numerous value-added endpoint designs are the largest target application for the FPGA-based designs.

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