How to build reliable FPGA memory interface controllers without writing your own RTL code!

As FPGA designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's more advanced FPGAs provide embedded blocks in every I/O that make the interface design easier and more reliable. These I/O elements are building blocks that, when combined with surrounding logic, can provide the designer with a complete memory interface controller. Nonetheless, these I/O blocks – along with extra logic – must be configured, verified, implemented, and properly connected to the rest of the FPGA by the designer in the source RTL code.

But, what if these difficult tasks were taken care of by the FPGA vendor? What if a designer could simply use a GUI to input the memory system parameters and generate RTL code without writing it from scratch? Finally, what if the physical layer interface was based on hardware verified designs? All this is now possible using the Memory Interface Generator (MIG) from Xilinx. This "How To" article will discuss the various memory interface controller design challenges and how to use the MIG to build a complete memory interface solution for your own application on a Virtex-4 FPGA.

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