Building high-speed FPGA memory interfaces

By Paul Evans, Altera Corp.  
pldesignline.com (September 02, 2009)

Building reliable, high-speed memory interfaces target FPGA I/O structures as well as intellectual property (IP) used within design software to allow rapid configuration of memory interfaces. These techniques use IP to help gain an extra timing margin at high speed operation

External double data rate (DDR) memory types are a common part of many FPGA designs. This article will examine the architecture behind the I/O blocks in high-end FPGAs (i.e. Altera's Stratix IV devices) and how these FPGAs are able to achieve 533 MHz or 1067 Mbps data rates. It also examines the tools that are used to build a memory interface, and provide a brief overview of the timing budget.

These FPGAs support the five leading double data rate memory types, that is DDR1, DDR2, and DDR3 as well as QDRII+ and RLDRAM as well as other memory interface types. RLDRAM is supported at rates of up to 1,600 megabits per second or 400 megahertz, QDRII+ at 1,400 megabits per second, and DDR3 at speeds of up to 533 megahertz or 1,067 megabits per second.

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