How to adapt traditional RTOSes to symmetric multiprocessing
By John Carbone, Express Logic, Inc.
Embedded.com, Dec 12 2005 (9:00 AM)
Mulltiprocessor (MP) and multicore System-on-Chip architectures are now beginning to be employed in a wide range of embedded consumer and communications systems. They are perceived as a way to enhance performance in applications requiring execution of multiple tasks without the demands on power consumed in a single processor configuration cranked up to its highest clock rate.
Typical of such applications are a set-top box designed to record several channels while sharing home movies across the Internet, or an in-car computer system doing navigation tasks while at the same time delivering backset video gaming, anong others.
But MP designs introduce programming complexity that can make them difficult to use and can threaten development schedules. Better software tools are needed to make MP development easier, and included among them is the operating system, which – when properly implemented -- has the unique capability of enabling an MP system to be programmed much like a single processor system.
But to make this possible, commercial providers of RTOSes - and the 50 percent or so of all developers who still build their own real time operating kernels - are faced with significant challenges. As the shift is made to more diverse, heterogeneous multiprocessing, the big questions facing developers include: what changes will have to be made to the applications developed for such environments, to the tools and the underlying OS structure.
It is clear that as designs with six, seven or more processing elements on a chip emerge, significant changes will have to be made. However, currently there is a large class of embedded applications in consumer electronics that allow the use of the well known symmetric multiprocessing (SMP) approach. Developed for server clusters and large computing applications, SMP does not require significant changes to the seasoned sequential, procedural single programming model.
When chosen with careful attention to real time performance, multithreading and real time interrupt response, even existing RTOSes can be used in such environments, While it will not be possible to achieve the theoretical maximum performance of an n-CPU device in a multiprocessor configuration (n*100%), significant incremental improvements are possible, ranging from 20% to even 90% under ideal conditions.
Embedded.com, Dec 12 2005 (9:00 AM)
Mulltiprocessor (MP) and multicore System-on-Chip architectures are now beginning to be employed in a wide range of embedded consumer and communications systems. They are perceived as a way to enhance performance in applications requiring execution of multiple tasks without the demands on power consumed in a single processor configuration cranked up to its highest clock rate.
Typical of such applications are a set-top box designed to record several channels while sharing home movies across the Internet, or an in-car computer system doing navigation tasks while at the same time delivering backset video gaming, anong others.
But MP designs introduce programming complexity that can make them difficult to use and can threaten development schedules. Better software tools are needed to make MP development easier, and included among them is the operating system, which – when properly implemented -- has the unique capability of enabling an MP system to be programmed much like a single processor system.
But to make this possible, commercial providers of RTOSes - and the 50 percent or so of all developers who still build their own real time operating kernels - are faced with significant challenges. As the shift is made to more diverse, heterogeneous multiprocessing, the big questions facing developers include: what changes will have to be made to the applications developed for such environments, to the tools and the underlying OS structure.
It is clear that as designs with six, seven or more processing elements on a chip emerge, significant changes will have to be made. However, currently there is a large class of embedded applications in consumer electronics that allow the use of the well known symmetric multiprocessing (SMP) approach. Developed for server clusters and large computing applications, SMP does not require significant changes to the seasoned sequential, procedural single programming model.
When chosen with careful attention to real time performance, multithreading and real time interrupt response, even existing RTOSes can be used in such environments, While it will not be possible to achieve the theoretical maximum performance of an n-CPU device in a multiprocessor configuration (n*100%), significant incremental improvements are possible, ranging from 20% to even 90% under ideal conditions.
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- HBM4 Controller IP
- IPSEC AES-256-GCM (Standalone IPsec)
Related Articles
- How to create energy-efficient IIoT sensor nodes
- How to reuse your IIoT technology investments - now
- How FPGA technology is evolving to meet new mid-range system requirements
- It's Not My Fault! How to Run a Better Fault Campaign Using Formal
Latest Articles
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor
- Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
- Leveraging FPGAs for Homomorphic Matrix-Vector Multiplication in Oblivious Message Retrieval