Formal, simulation, and AMBA verification IP combine to verify configurable powerline networking SoC
David Vincenzoni, R & D design manager, STMicroelectronics
Electronic Product Design & Test (November 21, 2013)
While wireless networking is a convenience, it is only valuable when it works. The HomePlug Broadband power line networking SoC is designed to enable networks over common power lines, extending the Internet to places where wireless networks cannot reach.
Such a product is subject to high schedule and cost pressures; we must constantly work to balance the development of cutting edge, differentiated capabilities with leveraging off-the-shelf, standard IP and interfaces and a myriad of peripherals.
By broadening our horizons and intermixing a formal analysis “app”, simulation, and assertion-based verification IP, my team and I obtained more complete results, faster and more efficiently than ever before. Some verification tasks naturally align with a given technology – for example, constrained random simulation is great for driving packet traffic and validating robustness to input noise, while formal is perfect for exhaustive analysis of complex logic and IP connectivity.
To read the full article, click here
Related Semiconductor IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- 1G BASE-T Ethernet Verification IP
- Network-on-Chip (NoC)
- Microsecond Channel (MSC/MSC-Plus) Controller
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
Related Articles
- How formal verification saves time in digital IP design
- Formal-based methodology cuts digital design IP verification time
- A Comparison of Assertion Based Formal Verification with Coverage driven Constrained Random Simulation, Experience on a Legacy IP
- Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP
Latest Articles
- Extending and Accelerating Inner Product Masking with Fault Detection via Instruction Set Extension
- ioPUF+: A PUF Based on I/O Pull-Up/Down Resistors for Secret Key Generation in IoT Nodes
- In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
- David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- RoMe: Row Granularity Access Memory System for Large Language Models