Formal, simulation, and AMBA verification IP combine to verify configurable powerline networking SoC
David Vincenzoni, R & D design manager, STMicroelectronics
Electronic Product Design & Test (November 21, 2013)
While wireless networking is a convenience, it is only valuable when it works. The HomePlug Broadband power line networking SoC is designed to enable networks over common power lines, extending the Internet to places where wireless networks cannot reach.
Such a product is subject to high schedule and cost pressures; we must constantly work to balance the development of cutting edge, differentiated capabilities with leveraging off-the-shelf, standard IP and interfaces and a myriad of peripherals.
By broadening our horizons and intermixing a formal analysis “app”, simulation, and assertion-based verification IP, my team and I obtained more complete results, faster and more efficiently than ever before. Some verification tasks naturally align with a given technology – for example, constrained random simulation is great for driving packet traffic and validating robustness to input noise, while formal is perfect for exhaustive analysis of complex logic and IP connectivity.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- How formal verification saves time in digital IP design
- The pitfalls of mixing formal and simulation: Where trouble starts
- Formal-based methodology cuts digital design IP verification time
- A Comparison of Assertion Based Formal Verification with Coverage driven Constrained Random Simulation, Experience on a Legacy IP
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience