Embedded flash process enhances performance: Product how-to
Jae Song, Dongbu HiTek
EDN (August 23, 2014)
Mobile phones and tablets have become natural extensions of billions of users worldwide. Considered an essential companion by many, these gadgets continue to push performance limits as they integrate enhanced nonvolatile memory and ever smarter power management. Thanks to a new embedded Flash (eFlash) process, fabless chip designers can now economically integrate better performing nonvolatile memory into mobile chips while conserving power. The new process is especially well suited for embedding flash into Touch Screen Controllers (TSCs) and Micro Controller Units (MCUs).
The graphs that follow detail the key specifications for the new eFlash process at the 0.13 micron node. Fabless chip designers who seek to embed nonvolatile memory would be wise to consider these parameters before releasing their designs to a foundry.
To read the full article, click here
Related Semiconductor IP
- NAND Flash Memory Controller with DMA
- LogicFlash Pro® Embedded Flash memory IP
- Flash Memory LDPC
- External Flash Memory Interface IP
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
Related White Papers
- Product how-to: Reliable SoC bus architecture improves performance
- Product How-to: Fully utilize TSMC’s 28HPC process
- Meeting Increasing Performance Requirements in Embedded Applications with Scalable Multicore Processors
- Using edge AI processors to boost embedded AI performance
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience