EDA in the Cloud Will be Key to Rapid Innovative SoC Design
By Mahesh Turaga, Cadence Design Systems
EETimes (August 22, 2021)
Simultaneous mega-trends are shaping multiple industries from aerospace and defense, automotive and high-tech to healthcare and others. These include 5G, autonomous vehicles, industrial internet of things (IIoT), electrification, hyperscale computing and artificial intelligence / machine learning (AI/ML). Add cloud to the mix, and we have another generational disruption that has driven business over the past decade and been further accelerated by our current global situation, changing the way we work, live, communicate and entertain. Cloud opportunities go far beyond flexible ubiquitous access.
In the preceding decade, the move towards cloud computing occurred primarily in sectors like retail and finance, with the advent of leading cloud vendors such as Amazon Web Services (AWS), Microsoft Azure, Google Cloud Platform and others accelerating the trend. In the electronic design automation (EDA) space, until recently, traditional concerns about security, protecting intellectual property (IP) and data outweighed the significant advantages offered by computing in the cloud — such as flexibility, scalability and productivity.
That is now changing, and the cloud-enabled value of each of those industries is driving the need for intelligent systems. We now see that the only way such systems can be created is by using cloud-enabled computing tools and methods. It is the “systems” that are driving the need for massively parallel computing with close-to-linear performance growth and virtually unlimited scalability while maintaining the highest level of accuracy. Those results are possible only in the cloud. With leading foundries in the space adopting cloud and acknowledging the security of cloud infrastructure by having their process design kits (PDKs) in the cloud, security concerns have by and large diminished.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related White Papers
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
- How to manage changing IP in an evolving SoC design
- It's Just a Jump to the Left, Right? Shift Left in IC Design Enablement
- The Growing Imperative Of Hardware Security Assurance In IP And SoC Design
Latest White Papers
- Reimagining AI Infrastructure: The Power of Converged Back-end Networks
- 40G UCIe IP Advantages for AI Applications
- Recent progress in spin-orbit torque magnetic random-access memory
- What is JESD204C? A quick glance at the standard
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience