DSP options to accelerate your DSP+FPGA design
Suhel Dhanani, Altera Corporation
EETimes (10/14/2010 2:56 PM EDT)
Although signal processing is usually associated with digital signal processors, it is becoming increasingly evident that FPGAs are taking over as the platform of choice in the implementation of high-performance, high-precision signal processing.
For many such applications, the choice generally boils down to using either a single FPGA, a FPGA with an associated DSP processor or a farm of DSP processors.
While it is generally understood that DSP processors can be programmed in C – leading to a much simpler development flow – this advantage is quickly dissipated when the design has to be partitioned across either multiple DSP processors or between a DSP processor and a FPGA. The truth is that a single DSP processor lacks the performance to do the signal processing required by most infrastructure systems.
This then requires system designers to make a choice between using multiple DSP processors or a FPGA. The latter choice almost always results in the lowest system cost/power implementation.
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- CXL 3.0 Controller
- ECC7 Elliptic Curve Processor for Prime NIST Curves
Related White Papers
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Introduction to the Philips’ LPC 2100 ARM 7-based microcontroller – the first standard microcontroller to integrate ARM-7 – and the first to use Philips’ new Memory Acceleration Module
- Using PLDs for Algorithm Acceleration - Faster, Better, Cheaper
- C-Language techniques for FPGA acceleration of embedded software
Latest White Papers
- TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs
- How a Standardized Approach Can Accelerate Development of Safety and Security in Automotive Imaging Systems
- SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
- Enabling Chiplet Design Through Automation and Integration Solutions
- Shift-Left Verification: Why Early Reliability Checks Matter