C-Language techniques for FPGA acceleration of embedded software
By David Pellerin (ImpulseC) and Kunal Shenoy (Xilinx)
Mar 31 2006 (14:19 PM), Courtesy of Programmable Logic DesignLine
Developers of embedded and high-performance systems are taking increased advantage of FPGAs for hardware-accelerated computing. FPGA computing platforms effectively bridge the gap between software programmable systems based on traditional microprocessors and systems based on custom hardware functions. Advances in design tools have made it easier to create hardware-accelerated applications directly from C language representations, but it is important to understand how to use these tools to the best advantage, and how decisions made during the design and programming of mixed hardware/software systems will impact overall performance.
This paper presents a brief overview of modern FPGA-based platforms and related software-to-hardware tools, then moves quickly into a set of examples showing how computationally-intensive algorithms can be written, analyzed and optimized for increased performance.
To read the full article, click here
Related Semiconductor IP
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
- UCIe RX Interface
- Very Low Latency BCH Codec
- 5G-NTN Modem IP for Satellite User Terminals
- 400G UDP/IP Hardware Protocol Stack
Related Articles
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- Software Infrastructure of an embedded Video Processor Core for Multimedia Solutions
- Open-Source Design of Heterogeneous SoCs for AI Acceleration: the PULP Platform Experience
- Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
Latest Articles
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- A Persistent-State Dataflow Accelerator for Memory-Bound Linear Attention Decode on FPGA
- VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
- PDF: PUF-based DNN Fingerprinting for Knowledge Distillation Traceability