Design Constraint Verification and Validation: A New Paradigm
June 18, 2007 -- edadesignline.com
Over the years, Electronic Design Automation (EDA) tools have matured considerably. They now aid in design and verification of all aspects of chip manufacturing. One area that has lagged behind is the validation of design constraints. While chip design, functional verification, timing verification and manufacturing have become highly automated, the writing and verification of design constraints has been largely a tedious, manual process.
Today, we have software that can manage, verify and even create design constraints. This allows designers to reduce design cycle times and improve the quality of the design constraints. Improved constraints mean higher quality silicon, especially at finer geometries like 90nm and below (Figure 1).
1. Today's Constraint Management tools can validate and generate constraints for all stages of the design flow.
An extension of constraint validation is exception generation. A constraint management tool can examine the netlist and find functional false paths. The tool must validate these with a proven formal engine to prove the paths can be declared false. Once the paths are proven as false, they can be removed from the cost-equation and static timing analysis of the synthesis and implementation tools. This frees the optimization engine to concentrate on real paths. The benefit is a smaller, faster, cooler design.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
- Verification IP for DisplayPort/eDP
- Wirebond Digital and Analog Library in TSMC 65nm
Related White Papers
- New Realities Demand a New Approach to System Verification and Validation
- System Verilog Macro: A Powerful Feature for Design Verification Projects
- Differentiation Through the Chip Design and Verification Flow
- Paving the way for the next generation of audio codec for True Wireless Stereo (TWS) applications - PART 5 : Cutting time to market in a safe and timely manner
Latest White Papers
- What tamper detection IP brings to SoC designs
- Analyzing Modern NVIDIA GPU cores
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
- Leveraging RISC-V as a Unified, Heterogeneous Platform for Next-Gen AI Chips
- Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core