Get control of ARM system cache coherency with ACE verification
Mirit Fromovich, Pete Heller, and Yoav Lurie, Cadence
EEtimes (8/9/2011 1:34 AM EDT)
In this Product How-Two article, the Cadence authors describe how to use the company’s Verification IP solutions framework to implement ARM’s AMBA 4 Coherency Extensions (ACE) in embedded SoC designs.
The challenges facing designers of the next generation of devices such as multimedia smartphones, tablets, and other mobile devices are many. They have to deliver highly responsive systems yet must also consume the least power possible—certainly no more than their competitors.
To achieve these goals, designers have been employing multi-processor architectures for many years. However, the need for even greater performance has exceeded the capability of current multi-processor/multi-cluster architectures.
Squeezing every last drop of performance and power out of these compute clusters is more important now than ever. One of the largest areas of opportunity for performance gains in multi-processor systems is in moving software-based cache-coherency management into hardware.
To read the full article, click here
Related Semiconductor IP
- NPU IP Core for Mobile
- NPU IP Core for Edge
- Specialized Video Processing NPU IP
- HYPERBUS™ Memory Controller
- AV1 Video Encoder IP
Related White Papers
- Fast, Thorough Verification of Multiprocessor SoC Cache Coherency
- ACE'ing the verification of a cache coherent system using UVM
- A Chip IP Integrator for System Level Design
- AMBA 4 ACE for Heterogeneous Multiprocessing SoCs
Latest White Papers
- Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
- Transition Fixes in 3nm Multi-Voltage SoC Design
- CXL Topology-Aware and Expander-Driven Prefetching: Unlocking SSD Performance
- Breaking the Memory Bandwidth Boundary. GDDR7 IP Design Challenges & Solutions
- Automating NoC Design to Tackle Rising SoC Complexity