Guide to VHDL for embedded software developers: Part 3 - ALU logic & FSMs
Peter Wilson
EETimes (7/25/2011 1:17 AM EDT)
Editor’s Note: In this series of articles based on his book – Design Recipes for FPGAs – Peter Wilson provides a basic quick overview of VHDL (VHSIC hardware description language) followed by examples of its use in describing - in HDL code form - functions familiar to most embedded software developers such as arithmetic logic units (ALUs) and finite state machines (FSMs). It is not intended as a comprehensive VHDL reference. For that, he recommends “Digital System Design with VHDL,” by Mark Zwolinski; ”VHDL: Analysis and modeling of digital systems,” by Zainalabedin Navabi or “Designer’s Guide to VHDL” by Peter Ashenden. This third part in a series describes how low-level logic and arithmetic functions can be implemented in VHDL to build simple arithmetic logic units and finite state machines.
A central part of microprocessors is the ALU (Arithmetic Logic Unit). This block in a processor takes a number of inputs from registers and as its name suggests carries out either logic functions (such as NOT, AND, OR and XOR) on the inputs,or arithmetic functions (addition or subtraction as a minimum).
To read the full article, click here
Related Semiconductor IP
- HBM4 PHY IP
- Ultra-Low-Power LPDDR3/LPDDR2/DDR3L Combo Subsystem
- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- VIP for Compute Express Link (CXL)
- HBM4 Controller IP
Related Articles
- Embedded Systems: Programmable Logic -> Programming enters designer's core
- Embedded Systems: Programmable Logic -> Common gateway networks enable remote programs
- Embedded Systems: Programmable Logic -> FPGAs don remote reprogram habits
- Embedded Systems: Programmable Logic -> Embarrassment of riches hinders proper use of Moore's Law
Latest Articles
- Making Strong Error-Correcting Codes Work Effectively for HBM in AI Inference
- Sensitivity-Aware Mixed-Precision Quantization for ReRAM-based Computing-in-Memory
- ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update
- A 14ns-Latency 9Gb/s 0.44mm² 62pJ/b Short-Blocklength LDPC Decoder ASIC in 22FDX
- Pipeline Stage Resolved Timing Characterization of FPGA and ASIC Implementations of a RISC V Processor