How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Allan Chin and Luciano Zoso, Stellamar
EETimes (1/18/2011 3:01 PM EST)
When we engineers look at the complexity of system design these days, we are challenged with cramming more functions into a smaller space, while consuming less power, and doing all of this in much shorter design cycles.
Efficient and effective analog design has always been a significant roadblock to hitting our deadlines; generally speaking, digital design and verification is much easier. This has certainly been true in our experience, which has involved spending the last 30 years learning the “art” of mixed-signal design.
Unfortunately, the ability to overcome the size and performance constraints of analog blocks is directly proportional to the mixed-signal engineer’s experience. Learning this art can take a lifetime. The time investment not only strains design cycles, but also hurts creativity, and it can be an impediment to cultivating a young, robust labor pool. The vast number of new graduates going into digital design as opposed to analog design is evidence of this. As a result, not much has truly been done to improve the underlying fabric of analog architecture and address inherent problems over the last 20 years.
To read the full article, click here
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
- 0.9V/2.5V I/O Library in TSMC 55nm
- 1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
Related White Papers
- Stellamar's all-digital, fully-synthesizable, analog-to-digital converters for Microsemi FPGAs
- Modeling high-speed analog-to-digital converters
- Understanding Interface Analog-to-Digital Converters (ADCs) with DataStorm DAQ FPGA
- LVDS ups A/D converter data rates
Latest White Papers
- What tamper detection IP brings to SoC designs
- Analyzing Modern NVIDIA GPU cores
- RISC-V in 2025: Progress, Challenges,and What’s Next for Automotive & OpenHardware
- Leveraging RISC-V as a Unified, Heterogeneous Platform for Next-Gen AI Chips
- Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core