A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach

David Elléouet¹ , Nathalie Julien², Dominique Houzet¹

Abstract :

Today and more tomorrow, Electronic system design requires to be concerned with the power consumption consideration. Currently, in a lot of design tools, the application power consumption budget is estimate after RTL synthesis. We propose in this article a methodology based on measurements allowing to model the application power consumption on FPGA with architectural and algorithmic parameters. So, The modeled applications can be added in a library in order to help the designer to determine quickly the best adequacy between high performances and low power consumption.

1) Introduction

The typical system design flow has known a paradigm shift with the re-using approach. An application can be now developed in a very short time with the association of existing IPs (Intellectual Properties). Although this design methodology enhances the designer efficiency and reduces the time-to-market, its weak point remains the power consumption consideration.

Current system power estimation is obtained after design place and route, e.g: XPOWER. At this level, when the power estimation exceeds the power budget, the designer must backtrack on architecture and algorithm IP parameters. This operation is time consuming and the power optimizations are not always obvious. Moreover, this estimation is not usable to design a new system. To improve the design flow effectiveness, it is necessary to raise the power estimator abstraction level [Rabaey1996].

In this paper, a methodology based on measurements is proposed for modeling the power consumption of existing IPs with high-level parameters. These models can be associated with IPs high-level descriptions in a library provided by the design tool. Thus, the designer can rapidly choose the best adequacy between algorithm and architecture in order to respect the IPs power consumption budget.

The paper is organized as follows: In section 2, the FLPA methodology used for modeling the IP power consumption is presented. Section 3 show how to measure the IPs power consumption. Section 4 present the method used to extract the IP power model from measurements. Some results obtained for various IPs on different FPGA family are given in section 5. Section 6 conclude this paper and present the future works.

2) Our IP Power Modeling Methodology

Recently, the FPGAs incorporate processor cores, arithmetic elements and memory blocks, in addition to the usual logic elements. They allow the realization of complex SOPC (System On Programmable Chip) by combining hardware and software IPs. So, we have chosen to use a FPGA in order to validate our high level IPs power modeling approach.

For modeling the IP power consumption on FPGA, we have applied the F.L.P.A (Functional Level Power Analysis) methodology, which was developed by [Lau2003] and allows to extract the processor power consumption model with a set of high level parameters [Julien2003].

Figure 1 : The FLPA methodology

This methodology is based on physical measurements inorder to guarantee realistic values with good accuracy.

The F.L.P.A methodology represented on figure 1 has four main parts, which are given below:

• Here, each IP is considered as a black box. A primary functional analysis helps the designer to determine which high-level parameters have an effective impact on the power consumption: relevant algorithmic and architectural parameters are then selected such as entropy in a picture, number of FFT points, filter order, clock frequency, data size and so on.

• Then, the power characterization step explicit the power consumption behavior (obtained by measurements) when each parameter varies independently.

• After curve fitting, the complete power model is obtained; it expresses the whole of power consumption variations related to all the parameters.

• Finally, the accuracy of the model obtained is validated against a new measurements set.

3) Power Measurement Method:

The FLPA methodology is based on power measurements. An automatic power measurement bench was developed in order to reduce the time of each scenario measurements.

As shown in figure 2, to measure the IP power consumption we use two FPGAs. In the first FPGA, we successively implement the various IP configurations. In the second, we place a stimuli generator. The frequency generator is used to provide the various frequencies to both FPGAs. The logic analyzer allows to test the IP functionality on chip. All the measurement equipment communicate with the host computer by GPIB bus. The measurement bench can be used by a distant computer through a LAN connection. The measurement procedure is done as follows:

• First, we program both FPGAs by the host PC using JTAG link.

• Then, for various parameters values and clock frequencies (0 to 80 MHz), we record the supply current consumed by the FPGA core in which IP are established.

• Finally, The power consumed is obtained as the product of the current measured with the FPGA core supply voltage.

Figure 2 : The FPGA power measurement bench

Both FPGA used in the measurement bench are not of the same family which are Virtex E and Virtex 2 pro. The interest here is to model the IP power consumption on different FPGA technologies.

4) Power Modeling Method

P_{IP =} P_{Dynamic +} P_Static         (1)

The IP power model is given by the equation (1). It is composed of two terms, which are the dynamic power (equation (2)) and the static power (equation (3)).

P_Static = S(High Level Parameters)+ P_FPGAPlan        (2)

Equation (2) is obtained by statistics analysis of power consumption measurements with a clock frequency of 0 MHz. This equation is a function of the high level parameters and the power consumed by the FPGA configuration plan. This last part depends on FPGA size and technology.

P_Dynamic  = D (High Level Parameters) x f_MHz      (3)

The static power is deduced from the other power consumption measurements in order to obtain equation (3), which is composed of clock frequency and the different high-level parameters.

Table 1: Maximum and average errors for each high-level power consumption model.

5) Results

This approach was applied to different IPs such as Xilinx's memory block [Ell2004], Filter Impulse Response application, Fast Fourier Transform and Locally Adaptive Resolution space coder. The LAR is an algorithm for image processing developed by [Bab2003].

Table 1 shows the maximum and average errors obtained with our high-level approach modeling against measurements for the different IPs on different FPGA families. The results obtained for the different experiments validate our approach. Furthermore, table 1 gives the parameter numbers for each model. With each models the power estimation is obtained easily. Thus, a good adequacy between architecture, algorithm, and power consumption can be found with our model at early design stage.

6) Conclusion and Future Works

We have presented here a methodology which allows to model the power consumption of existing IPs on FPGA. The interest of our approach is to enhance the designer efficiency. During the first step of a system design flow, these models help the designer to develop an application under a power constraint. The time consuming in design backtrack is strongly reduced and model estimation is reusable for designing a new system. Future works will consist in increasing the IPs library, in particular those dedicated to communication such as NoC. A user web access will be develop for the power measurement bench. Therefore, we will offer the possibility to an external designer to apply our methodology and to model their IPs.

References:

[Rabaey1996] J. M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publisher, ISBN 0-7923-9630-8, 1996.

[Lau2003] J. Laurent and N. Julien and E. Senn and E. Martin, Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors, IEEE DATE, 2004.

[Julien2003] N. Julien and J. Laurent and E. Senn and E. Martin, Power consumption modeling and characterization of the TI C6201, IEEE Micro Volume 23, Issue 5. Page(s): 40 - 49, Sept-Oct 2003.

[Ell2004] D. Elléouet and N. Julien and D. Houzet and J. G. Cousin and E. Martin, Power Consumption Characterization and Modeling of Embedded Memories in Xilinx Virtex 400E FPGA, EUROMICRO Symposium on DIGITAL SYSTEM DESIGN, 2004.

[Bab2003] M. Babel and O. Deforges and J. Ronsin, Lossless and Lossy Minimal Redundancy Pyramidal Decomposition for Scalable Image Compression technique, 4th IEEE International Conference on Multimedia and Expos (ICME) , 1999.

Laboratoire I.E.T.R¹, UMR CNRS 6164, Institut National des Sciences Appliquées, 35043 RENNES Cédex, France. david.elleouet@ens.insa-rennes.fr

Laboratoire L.E.S.T.E.R², FRE CNRS 2734, Université de Bretagne Sud, 56321 Lorient Cédex, France. nathalie.julien@univ-ubs.fr