YorChip and Sofics Expand UCIe PHY Across TSMC Nodes

Enabling low-cost, low-latency chiplet connectivity for Physical AI at the edge

AALTER, BELGIUM / SAN JOSE, CALIFORNIA – January 21, 2026 – Sofics® bv, a global leader in on-chip electrostatic discharge (ESD) and specialty I/O solutions, today announced a partnership with YorChip Inc., a Silicon Valley startup developing ultra-compact, low-cost chiplets for the emerging Physical AI market.

The collaboration focuses on porting YorChip’s 100% digital UCIe PHY across multiple TSMC process nodes: from 28nm planar CMOS to the most advanced 2nm Nanosheet technology. It will enable broader adoption and faster commercialization of interoperable chiplet communication IP.

YorChip’s UCIe PHY is purpose-built for space- and power- constrained edge AI applications, delivering lower cost and latency than traditional data center PHYs. As part of the collaboration, Sofics brings its silicon-proven IP and design expertise across CMOS, FinFET and Nanosheet nodes, ensuring robust, high-performance interfaces while accelerating scaling across process generations.

“Time-to-market is critical for Physical AI,” said Kash Johal, CEO and founder of YorChip. “Sofics is an ideal partner, flexible, experienced, and fast. Their 15-year track record supporting advanced TSMC nodes is helping port and validate our UCIe PHY across the full node spectrum. This partnership accelerates the availability of our chiplet IP to a broader chiplet ecosystem beyond HPC/Data Center markets.”.

“Sofics is an ideal partner, flexible, experienced, and fast. Their 15-year track record supporting advanced TSMC nodes is helping port and validate our UCIe PHY across the full node spectrum”

Kash Johal, CEO and founder of YorChip

“YorChip’s vision for low-cost, multi-node chiplet platforms aligns perfectly with our mission to deliver robust and differentiated I/O solutions,” said Koen Verhaege, CEO of Sofics. “Having supported thousands of IC designs across mature and leading-edge nodes, we’re proud to help bring Physical AI-optimized chiplet interfaces to market faster.”

“Having supported thousands of IC designs across mature and leading-edge nodes, we’re proud to help bring Physical AI-optimized chiplet interfaces to market faster”

Koen Verhaege, CEO of Sofics

“Our customers are asking for broad node support with optimized cost, power and latency,” said Brian Faith, CEO of QuickLogic. “A fully digital UCIe PHY that removes interoperability and cost barriers across nodes is a significant enabler for the chiplet ecosystem.”

“Our customers are asking for broad node support with optimized cost, power and latency”

Brian Faith, CEO of QuickLogic

The combined solution will be featured at Chiplet Summit 2026, where both companies will present technical highlights and roadmap plans. Sofics and QuickLogic have separate booths at the Chiplet Summit in Santa Clara on February 17-19, 2026.

With this partnership, YorChip and Sofics aim to lower integration barriers for chiplet-based systems, and other edge-focused AI applications.

About Sofics

Sofics (www.sofics.com) is a leading independent provider of semiconductor IP for on-chip ESD, specialty I/O and reliability solutions. Sofics IP is integrated in thousands of commercial IC designs across CMOS, FinFET, BCD and SOI processes

About YorChip

YorChip (www.yorchip.com) is focused on enabling Chiplets with power and cost optimized interconnect IP and facilitate development of 3^rd party IP Chiplets to enable customers to get to market faster at lower cost. The company is based in San Ramon California and has partners worldwide