VSIA readies four SoC design specs

VSIA readies four SoC design specs
By Richard Goering, EE Times
February 1, 2000 (3:33 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000201S0029

SANTA CLARA, Calif. — Adding more meat to its portfolio of technical specifications for system-on-chip (SoC) design, the Virtual Socket Interface Alliance (VSIA) is preparing to publicly release two new specifications and is going into member review with two others. The new activity came to light at an "SoC Symposium" led by VSIA at this week's DesignCon 2000 show.

Pending VSIA board approval this Friday (Feb. 4), VSIA will publicly release a behavioral interface specification from the system-level design development working group (SLD DWG), and a basic and peripheral virtual component interface specification from the on-chip bus (OCB) DWG. Going into member review are the virtual component transfer (VCT) specification 2.0, and a new intellectual property (IP) "tagging" scheme, designed to mark virtual components so ownership can be established.

At the symposium, Howard Sachs, president of VSIA, said the o rganization has made "good progress" and noted that VSIA has already released 10 specifications, in addition to the four going into member review or final release. Sachs said VSIA has become a "coalescing force" in the industry by bringing different organizations together.

The new system-level design interface spec is part of a family of documents aimed at easing the "iterative refinement" of high-level designs, said Chris Lennard, chairman of the SLD DWG. Lennard said the working group has two primary goals: mutual comprehension of system-level concepts; and interoperability of models.

The group's first effort in the comprehension area was the SLD taxonomy document released last year. This document seeks to establish a common way to describe different types of high-level models.

Workable spec

The other part of the comprehension theme is the new interface document, which outlines a hierarchical way to separate internal behavior from interface protocols. It defines the various ways in which a "protocol block" might communicate with a "behavioral block," as well as with the external world. "We're trying to push an executable spec, not a paper spec," said Lennard.

To help drive interoperability, the SLD DWG has two other specifications in the works. One outlines standard data types, and is closely aligned with the System C class library proposed by Synopsys and CoWare, Lennard said. The other specification will set forth an application programming interface for instruction-set simulation. Both are expected in the first half of 2000.

The OCB group, meanwhile, is working to define what Sukarno Mertoguno, DWG co-chairman, termed "bus-independent interfaces." That working group decided some time ago that mandating a single, standard on-chip bus won't work.

The focus has thus shifted to defining various aspects of a virtual component interface (VCI). The specification going into public release defines a two-wire "peripheral VCI" that supports read, write, and burst modes, along w ith error reporting. It also describes a four-wire "basic VCI" that supports read, write, and read-exclusive functions; packet and packet-chain transactions; and error reporting.

Still in the works is an "advanced VCI," which will add optional signals to support multiple packets, extended error/status reporting, arbitration latency hiding, user-defined commands, and multi-threading.

An audience member at the DesignCon symposium expressed concern about VSIA requiring extra wires, but that's not really the case, said Larry Rosenberg, VSIA technical committee chairman. "We're standardizing what people already use, so different people's stuff can play together," he said.

The OCB DWG is also working on a specification for a "transaction language" that will more closely connect system-level design with hardware implementation. It will also help bring verification to a higher level of abstraction, Mertoguno said.

The aim of the VCT DWG is to facilitate the "pervasive transfer and exchange of virtua l components," said Takeshi Fuse, DWG chairman. The group is envisioning a worldwide, Internet-based infrastructure allowing the hand-off of IP from creators to integrators. The already-released VCT 1 specification provides a checklist of items that should be included in the transfer.

The new VCT 2 spec, now going into member review, aims at setting forth a common nomenclature or terminology for virtual component (VC) "profiling." One intent is to facilitate the search process for IP using online catalogs. A VCT 2X specification, which will follow VCT 2, identifies the actual data format for VC exchange. Further down the road is VCT 3, an IP packaging standard.

VSIA's manufacturing test DWG doesn't have any new specifications coming out this week, but it's working hard to define common test data formats and guidelines for design for test, said R. Chandramouli, DWG chair. The group has already released the Test 1.1.0 standard, which describes a test data interchange format and design-for-test guideli nes.

Additionally, the group is closely collaborating with the IEEE P1500 group to come up with a "test access architecture" that will define how to access IP blocks. VSIA expects to endorse IEEE P1500 as soon as it becomes a standard. "With this, we want to make sure test reuse becomes a reality," said Chandramouli.

Publicly-released VSIA specifications are available at the VSIA Web site. Non-VSIA members are charged a nominal fee.