ViASIC Announces 12th Tape-out for ViaMask Standard-Metal Library
Durham, NC - June 27, 2005 - ViASIC Inc. today announced the successful tape-out of the first dozen chips using the ViaMask standard-metal libraries. Standard-metal uses pre-designed logic along with pre-designed routing. A design’s RTL is configured using a single via layer. The ViaMask standard-metal fabric offers excellent densities and routability while yielding standard-cell-like clock speeds and power consumption.
Because the ViaMask logic, memory, and routing are pre-characterized, design closure of timing, signal integrity, and power is much simpler than standard cell. By using ViaMask, mask costs can be up to 30x less, schedule costs are significantly lower, and design respins do not pose a problem. ViaMask customers can get their products to market quickly by creating an initial version before final specs are set. ViaMask customers can add or change a part's features, to target different markets or quickly add customer-specific features.
About ViaMASK
ViaMASK is a single via layer configuration solution, which can reduce NRE charges and fabrication cost by more than 90% compared to standard-cell design. This patented fabric provides easy design closure while providing a dense, high-performance fabric of interwoven configurable RAM and logic. The ViaMask standard-metal libraries have been used to build configurable SOCs as well as structured ASICs.
About ViASIC Inc.
ViASIC is a privately held EDA company and the leading provider of standard-metal tools and technologies. The company’s patented ViaMask fabric is a complete library for building platform ASICs or embedding single via layer configurable sections into an SoC. ViASIC also offers ViaPath, a robust physical design solution for via-configurable fabrics. ViASIC is located at 2635 Meridian Parkway, Durham, NC 27713. Telephone 919-767-6941, Fax 919-767-6933
www.viasic.com
Related Semiconductor IP
- Flexible Pixel Processor Video IP
- Bluetooth Low Energy 6.0 Digital IP
- MIPI SWI3S Manager Core IP
- Ultra-low power high dynamic range image sensor
- Neural Video Processor IP
Related News
- ViASIC Introduces Industry's First Two-Mask Standard Metal Fabric for Re-configurable SOC Design; DuoMask Patented Technology Provides a Complete Solution for All Processes
- Alphacore To Develop Rad-Hard CMOS Standard Cell Library, Meeting DOD Standards, For U.S. Navy
- Agile Analog launches new Digital Standard Cell Library
- SilTerra Leverages Silvaco's Library Characterization and Optimization Tools to Boost Efficiency in the Development of its Foundry Standard Cell IPs
Latest News
- Cyient Semiconductors Enters Strategic Channel Partnership with GlobalFoundries
- Aion Silicon Successfully Completes ISO 9001 and ISO/IEC 27001 Surveillance Audit, Strengthening Commitment to Quality and Security
- Baya Systems Awarded Globally Recognized ISO 9001:2015 Certification for Quality Management by TÜV Rheinland
- Si2 Announces Creation of the Si2 LLM Benchmarking Coalition
- Qualitas Semiconductor Signs Licensing Agreement with Chinese SoC Company for DSI-2 Controller and MIPI PHY IP