Verification answers sought for SoC designs

Verification answers sought for SoC designs
By Nicolas Mokhoff, EE Times
March 23, 2000 (4:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000323S0029

SANTA CLARA, Calif. — The verification of intellectual property (IP) blocks makes up two-thirds of the job of integrating such blocks into a system-on-a-chip (SoC) design. A panel at this week's IP2000 conference shed some light on how that verification chore can be made less gruesome and take less effort.

"In 1995, ninety percent of ASICs worked the first time out," said Phil Dworsky, director of marketing of Synopsys Inc.'s Design Reuse Group. "Today, with nine blocks on an SoC, which worked correctly 90 percent of a time from the start, the formula works out to be that these types of chips would work correctly only 39 percent of the time as one chip."

Dworsky cited the examples of five IP cores to illustrate the effort involved in designing and verifying IP blocks. The verification effort for the 8051 controller, the PCI interface, MPEG, USB2 and PCI-X took up 35-to-61 percent of the overall design and implementation tasks. "And there' s no straight correlation between the verification effort and the size of the block," he said. "For example, the largest core — the MPEG core, which occupies 85-k gates — takes only 44 percent of verification time vis-a-vis the design tasks for the chip."

Panelists from Tensilica, Intrinsix, and Palmchip agreed with Dworsky's assertion that this situation is untenable. In contrast, Won Rhee, a design/verification engineer at Agilent Technologies (Palo Alto, Calif.), offered a concrete plan for verifying IP blocks: "Our approach is based on the notion that every IP block needs to be shipped with its own verification data. We need to apply an object-oriented approach to what I call integration vectors."

Agilent's integration vectors consist of three components: alive vectors to check connectivity; typical/peak vectors that monitor resources; and vectors that target specific areas of a block. "Our software simulation is a framework for creating models, vectors and a testbench," Won Rhee said. "A well-defined vector testbench interface decouples vectors from the testbench, enabling verification reuse for other IP blocks."

Robin Bhagat, vice president of SoC technology at Palmchip (San Jose, Calif.), identified a platform for system-on-a-chip designs that consist of basic blocks upon which new IP blocks are "attached." A new IP block needs to talk to a processor, an interrupt controller, and a DMA controller that in turns talks to memory, Bhagat said. Having these defined interfaces limits the verification chore when integrating a new IP block.

That approach raised a question in the audience: When is it appropriate to apply formal verification techniques to IP integration? When the blocks are neatly defined and the interfaces are clean, which is rare, the panel answered.

Ashish Dixit, director of VLSI design at Tensilica (Santa Clara, Calif.), a developer of configurable microprocessor cores, agreed that formal verification can only be applied to well-defined IP blocks. "For IP integra tion the verification needs to be functional, not formal. Too many uncertainties exist at the interface among blocks." Dixit admitted that Tensilica's configurable core approach places extra burdens on verification. "It takes an enormous amount of verification for a moving target such as a configurable IP, up to three to four times the design effort," he said.

Jim Gobes, president and cofounder of Intrinsix (Westboro, Mass.), an ASIC design service company that specializes in SoC integration, made it plain that "nothing substitutes for experienced designers and verification engineers, irrespective of whether one uses functional or formal verification techniques." What it comes down, Gobes said, is that designers need a better methodology that includes a verification strategy at the beginning of a design.

Number one priority

When probed by Synopsys' Dworsky about how many people in the audience have an official verification plan for SoC designs, one person raised his hand. Dworsky's re action was swift and to the point: "Such a plan is the number one priority for designers to write up when architecting the chip." That, and code coverage — the amount of chip area that is covered by the written verification code — are essential for chips if they are to be shipped out the door in the desired market window, Dworsky said.