UMC rolls out 90-nm process, says pilot production due in 1Q 2003

UMC rolls out 90-nm process, says pilot production due in 1Q 2003
By Mark LaPedus, Semiconductor Business News
June 7, 2002 (4:09 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020607S0068

SANTA CLARA, Calif. -- During a technology conference here today, Taiwan's United Microelectronics Corp. (UMC) officially announced its 90-nm (0.09-micron) process, equipped with copper interconnects, low-k dielectrics, as well as a silicon-on-insulator (SOI) option.

UMC's 90-nm process--dubbed L90--will move into “early product tape-out” in the third quarter of 2002, with pilot production slated for the first quarter of 2003, said Fu Tai Liou, vice president of worldwide marketing and sales for the Hsinchu-based silicon foundry company.

The company's 90-nm offering is roughly on the same timetable as its rival in the foundry business--Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), according to analysts. Recently, TSMC also announced its 90-nm process, with plans to move into "risk production" by the third quarter of this year. Volume production is slated by year's end and well into 2003.

In a briefing with press and analysts here thi s morning, Liou declined to comment on which foundry company is leading the technology race, but he did say that the 90-nm market is still in its infancy. “90-nm is still in the very early stages in the market,” Liou told SBN in a brief interview after the press event.

Analysts believe the technology race is too close to call. “I still believe that it's a close race between the two leading dedicated foundries in TSMC and UMC,” said James Hines, who tracks the foundry market for Dataquest Inc. in San Jose.

“My perception is that TSMC is slightly ahead,” Hines said. “The other foundries, including Chartered, are significantly behind,” he said, referring to Singapore's Chartered Semiconductor Manufacturing Pte. Ltd.

UMC appears to be offering a number of 90-nm processes for various applications. But basically, the company's technology features copper interconnects and a low-k value of 2.7. Like its 130-nm (0.13-micron) process, UMC will use a “modified” version of CVD-based, low-k technology from Novellus Systems Inc., Liou said.

UMC will also migrate to 193-nm lithography tools to handle the critical layers for its 90-nm chips. It will use 193-nm tools from two vendors--ASML Holdings N.V. of the Netherlands and Nikon Inc. of Japan.

UMC's 90-nm logic process, dubbed L90 IP9M, is a 1- to 1.2-Volt technology, with gate lengths ranging from 0.08- to 0.045-micron. The nine-metal, single-poly process also features a gate-dielectric thickness of less than 14-16 angstroms. Propagation delays range from 20-ps to less than 7-ps, depending on the process version.

It will also offer a 90-nm mixed-mode process, with pilot production due in the second quarter of 2003. The company also will offer a 90-nm embedded DRAM process, dubbed eD90 and eD90s, which will move into production in the third quarter of 2003 and 2004, respectively