TSMC Goes Photon to Cloud
Rick Merritt, EETimes
October 4, 2018
SAN JOSE, Calif. — TSMC taped out its first chip in a process making limited use of extreme ultraviolet lithography and will start risk production in April on a 5nm node with full EUV. Separately, the foundry forged partnerships with four partners to support online services for back-end chip design.
The foundry’s update showed area and power gains continue in its leading-edge nodes, but chip speeds are no longer advancing at their historic rate. To compensate, TSMC gave an update on a half-dozen packaging techniques it is developing to speed connections between chips.
To read the full article, click here
Related Semiconductor IP
- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- TSMC CLN5FF GUCIe LP Die-to-Die PHY
- Flipchip 1.8V/3.3V I/O Library with ESD-hardened GPIOs in TSMC 12nm FFC/FFC+
Related News
- Cadence Partners with TSMC to Power Next-Generation Innovations Using AI Flows and IP for TSMC Advanced Nodes and 3DFabric
- Synopsys Collaborates with TSMC to Drive the Next Wave of AI and Multi-Die Innovation
- Innosilicon to Showcase High-Speed Interface IP and Advanced SoC Solutions at the 2025 TSMC OIP Ecosystem Forum
- GlobalFoundries Licenses GaN Technology from TSMC to Accelerate U.S.-Manufactured Power Portfolio for Datacenter, Industrial and Automotive Customers
Latest News
- PGC Strengthens Cloud and AI ASIC Acceleration with Synopsys’ Next-Generation Interface and Memory IP on Advanced Nodes
- IntelPro Licenses Ceva Wi-Fi 6 and Bluetooth 5 IPs to Launch AIoT Matter-Ready SoCs
- VeriSilicon and Google Jointly Launch Open-Source Coral NPU IP
- proteanTecs Appoints Noritaka Kojima as GM & Country Manager and Opens New Japan Office
- QuickLogic Reports Fiscal Third Quarter 2025 Financial Results