TSMC's R&D boss addresses 40-nm yields, high-k, litho
Mark LaPedus, EETimes
(02/24/2010 3:41 PM EST)
SAN JOSE, Calif. -- At the TSMC Japan Executive Forum in Yokohama this week, Shang-Yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), addressed several issues about the silicon foundry giant. Chiang discussed TSMC's 40-nm capacity, yield issues, high-k and lithography. EE Times obtained a transcript of the presentation. Here's some of the issues discussed:
To read the full article, click here
Related Semiconductor IP
- NFC wireless interface supporting ISO14443 A and B with EEPROM on SMIC 180nm
- DDR5 MRDIMM PHY and Controller
- RVA23, Multi-cluster, Hypervisor and Android
- HBM4E PHY and controller
- LZ4/Snappy Data Compressor
Related News
- TSMC 2nm yields nearly ready for mass production
- TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
- TSMC shuns high-NA EUV lithography
- National to use SiidTech's Silicon Fingerprinting to boost chip yields
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack