TSMC's R&D boss addresses 40-nm yields, high-k, litho
Mark LaPedus, EETimes
(02/24/2010 3:41 PM EST)
SAN JOSE, Calif. -- At the TSMC Japan Executive Forum in Yokohama this week, Shang-Yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), addressed several issues about the silicon foundry giant. Chiang discussed TSMC's 40-nm capacity, yield issues, high-k and lithography. EE Times obtained a transcript of the presentation. Here's some of the issues discussed:
To read the full article, click here
Related Semiconductor IP
- UCIe D2D Adapter & PHY Integrated IP
- Low Dropout (LDO) Regulator
- 16-Bit xSPI PSRAM PHY
- ASIL B Compliant MIPI CSI-2 CSE2 Security Module
- SHA-256 Secure Hash Algorithm IP Core
Related News
- TSMC 2nm yields nearly ready for mass production
- TSMC shuns high-NA EUV lithography
- National to use SiidTech's Silicon Fingerprinting to boost chip yields
- Date yields testimonials and processor cores
Latest News
- Alchip Appoints Freddy Engineer Chief Business Officer and North America General Manager
- Perceptia Devices and Dolphin Semiconductor Partner to Deliver Best-in-Class IP Portfolio Covering Power Management, Clocking, High-Quality Audio and In-Situ Monitoring
- TSMC Chases Soaring AI Demand
- EU DARE Project Is Scrambling to Replace Codasip
- Sofics and Alcyon Photonics Partner to Support Next-Generation Photonic Systems