TSMC's R&D boss addresses 40-nm yields, high-k, litho
Mark LaPedus, EETimes
(02/24/2010 3:41 PM EST)
SAN JOSE, Calif. -- At the TSMC Japan Executive Forum in Yokohama this week, Shang-Yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), addressed several issues about the silicon foundry giant. Chiang discussed TSMC's 40-nm capacity, yield issues, high-k and lithography. EE Times obtained a transcript of the presentation. Here's some of the issues discussed:
To read the full article, click here
Related Semiconductor IP
- Bluetooth Low Energy 6.0 Digital IP
- Ultra-low power high dynamic range image sensor
- Flash Memory LDPC Decoder IP Core
- SLM Signal Integrity Monitor
- Digital PUF IP
Related News
- TSMC 2nm yields nearly ready for mass production
- TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production
- TSMC shuns high-NA EUV lithography
- National to use SiidTech's Silicon Fingerprinting to boost chip yields
Latest News
- Intel facing another crossroads: 18A or 14A process node
- Creonic Successfully Renewed its ISO 9001:2015 Certification
- Silvaco Strengthens Leadership Team with Three Industry Veterans to Drive Innovation and Growth
- JFE Shoji Electronics Signs Sales Agent Agreement with Andes Technology
- Mixel Supports Automotive SerDes Alliance (ASA) Motion Link SerDes IP