TSMC's R&D boss addresses 40-nm yields, high-k, litho
Mark LaPedus, EETimes
(02/24/2010 3:41 PM EST)
SAN JOSE, Calif. -- At the TSMC Japan Executive Forum in Yokohama this week, Shang-Yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), addressed several issues about the silicon foundry giant. Chiang discussed TSMC's 40-nm capacity, yield issues, high-k and lithography. EE Times obtained a transcript of the presentation. Here's some of the issues discussed:
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