Toshiba cuts capacitor from DRAM cell design

Toshiba cuts capacitor from DRAM cell design
By Yoshiko Hara, EE Times
February 7, 2002 (2:40 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020207S0064

TOKYO — Toshiba Corp. has developed a one-transistor, no-capacitor cell structure that it claims solves the difficulties encountered in producing DRAMs in sub-0.1-micron process technology. The company presented the approach at the International Solid-State Circuits Conference in San Francisco this week.

A conventional DRAM cell consists of one transistor and one capacitor. But when a DRAM is processed at below 0.1 micron, this structure becomes a bottleneck. Even if the transistor shrinks, the capacitor has to maintain a certain capacity. In order to do so, the capacitor has to be formed deeper and deeper in a trench-cell structure, or stacked higher and higher in a stacked structure.

"To solve this bottleneck, new approaches have been proposed, but those approaches require new materials or complex cell structures," said Takashi Ohsawa, senior specialist of the advanced memory design group at Toshiba Memory Division. "The cell structure named floating-body cell that we've developed has a simple structure in the smallest size of 4F², does not require new material and is scalable, though it is not nonvolatile," Ohsawa said.

The floating-body cell (FBC) is formed on a silicon-on-insulator (SOI) wafer and consists of one MOSFET, whose body is electrically floating. Making use of the floating body, a charge (holes for nMOS) is stored in and drawn out from the body, which functions like the capacitor in a conventional DRAM cell.

"To design circuitry on SOI, a new design was needed because of this floating body, which was a kind of barrier to shift SOI. On the contrary, the FBC makes use of the floating body. The FBC is quite a suitable cell structure for SoC [system-on-chip] on SOI," Ohsawa said.

FBC is an nMOS transistor fabricated on an SOI substrate, which consists of a p-substrate, an n+ diffusion layer, a buried oxide layer and a silicon layer on the top. The source of the MOS transistor formed in the top silicon lay er is tied to a grounded source line, the drain to a bit line and the gate to a word line. Polysilicon pillars standing inside the shallow trench isolation on the n+ diffusion layer are biased at a minus voltage to make holes in the bodies. Those pillars serve as stabilizing capacitors coupled to the body to enhance the signal and extend retention time.

With this structure, a signal threshold of 250 millivolts is observed without a capacitor. In the future, it may be possible to take away the pillars and the n+ diffusion layer to make the structure simpler, Ohsawa said.

The FBC cell showed a data retention time of several seconds at a temperature of 30°C and 100 milliseconds at 85°C. "This figure is not satisfactory for the requirement of a standalone DRAM, but enough for embedded DRAM requirements," Ohsawa said. "For general-purpose DRAMs, the retention time needs to be more than one second at 85°C. We are working on it and have a strategy to solve this problem," he said.

The fi rst product that Toshiba engineers are targeting is a system-on-chip device that integrates the FBC DRAM using a 70-nanometer (0.07-micron) process. The first product will have several hundred Mbit FBC DRAMs embedded with logic and will be offered in 2004.