The CTO interview: with Ivo Bolsens of Xilinx

Peter Clarke
(12/16/2004 10:58 AM EST)

  Silicon Strategies caught up with Ivo Bolsens, chief technology officer of FPGA company Xilinx Inc., at the Intellectual Property and System on Chip conference in Grenoble, France, where Bolsens presented a keynote speech. Peter Clarke asked about some of the trends and development directions Bolsens sees for FPGAs which, at the high-end, are turning into complex design platforms that can be programmed in software as well as being configured in hardware.

Silicon Strategies: It is well known that putting a function down in FPGA is less efficient in die area than fully diffused approaches. But does the scaling of minimum geometries under Moore's Law favor field programmable gate arrays, or ASIC and System-on-Chip approaches?

Ivo Bolsens: FPGAs really benefit from scaling, partly because they are inherently regular. But they also protect designers from having to deal with deep-sub-micron issues. And Xilinx was able to introduce 90-nanometer manufacturing in March 2003. All our products are on 90-nm now. You can have more efficient use of transistors if you have regular structure.

Silicon Strategies: You've spoken of the need to re-label FPGAs "programmable platforms". So which is going to take precedence; the FPGA with an embedded diffused function, or the custom system-chip with an embedded patch of FPGA?

Ivo Bolsens: Well of course there's not just two options to choose between. There will be a trade-off curve and different applications will benefit at different points along it.

FPGAs are the innovator's dilemma. At first it was thought that they would only be used for prototyping; and then it was thought that they were only the poor engineer's ASIC.

But we are seeing a good take up of embedded functions. Seven out of ten of our customers use the gigabit transceivers that we offer. One in three customers use the DSP hard IP.

But the distributed embedded memory is probably the most important development from Xilinx. It is also remarkable that we have supplied more than 10,000 embedded development kits for use with MicroBlaze or PowerPC.

Silicon Strategies: MicroBlaze is your own design of 32-bit RISC processor intended for soft implementation in FPGA, while Xilinx also puts IBM PowerPC processors diffused on to some of its FPGA silicon slices. But you have also licensed IBM to use your FPGA architecture in its SOCs. Why didn't that happen before?

Ivo Bolsens: Well, ASIC designers cannot afford to define custom chips for every application. It has to do with the cost of NRE [non-recurring engineering] for chip development. So, for example, one ASIC with an FPGA patch could meet multiple standards.

And I think that any time before the 90-nanometer generation a reasonable amount of FPGA fabric would have dominated the cost of the silicon. So when introducing flexibility, embedded FPGA is going to become more relevant as we move to smaller dimensions. I think it will flourish at the 65-nanometer manufacturing node.

Silicon Strategies: What is the status of reconfigurable logic?

Ivo Bolsens: It's a great technology that can really set engineers' imaginations running. And programming of FPGAs in the field is used by 80 percent of Xilinx customers. One Japanese customer working on wireless infrastructure used FPGAs for a wireless basestation. Two others used ASICs. The first company was able to keep its basestations in the field and upgrade their 2G infrastructure. It has been calculated it saved them an investment of about US$1 billion.

And in-the-field configuration is going to play a more important role as standards are written around that capability. Software Defined Radio [SDR] is working on a standard comprising five clusters each made up of 20 so-called waveforms, which are profiles of carrier frequency, modulation scheme and protocol stack. SDR requires the hardware to sort through the possibilities and adapt itself to make a connection.

And beyond that I see reconfiguration playing a role in fault-tolerant and self-healing systems. Single-event upset is becoming more relevant to all forms of logic as dimensions scale down. Hardware could monitor itself and repair itself if there is change or a fault.

Silicon Strategies: People download software and drivers all the time. Why has downloadable hardware not been a hit with designers and users?

Ivo Bolsens: I suppose there are issues of product integrity and security that count against downloadable hardware, even though FPGA bit-streaming security has been raised.

You need a trusted provider and you need a well-understood methodology. From a technical point of view it's available now. It takes time for the business infrastructure to develop around that.

Silicon Strategies: What about soft processors versus hard processors?

Ivo Bolsens: It's amazing to think that with MicroBlaze you can get a 150 dhrystone MIPS processor on to 75 cents of silicon. And you could put hundreds of these soft processors into a high-end FPGA. So, if you don't need too much processing power MicroBlaze might be the way to go.

Meanwhile that PowerPC [diffused on FPGA] is far more efficient than a separate device because you can build a custom interface that can be hundreds of pins or channels wide.

Silicon Strategies: What scope is there for EDA to improve FPGA design, power efficiency?

Ivo Bolsens: There's lots of scope and EDA needs to address the complexity of modern FPGAs. An API [application programming interface] layer that allows people to work at a higher level would be beneficial; an API layer for DSP applications, another for networks and so on. The API should abstract away the underlying detail.

We have it in a way within the EDK [Embedded Development Kit], which allows for simple FIFO communication between processors. That's a first step.

Silicon Strategies: What are the hot R&D topics for Xilinx?

Ivo Bolsens: In general terms the top one is ease-of-use. We want to make FPGA design a programming experience akin to "edit, compile, debug". It is still too much of a hardware design experience. Higher-level design could open FPGAs up to the software community.

The next topics are low-cost and low-power.

Intrinsically FPGAs are not too bad on dynamic power. Obviously, it is not as good as an ASIC. If you can afford an ASIC you should probably do it, but you miss out on flexibility and fast time to market. But it is the static power that is not so good in FPGA.

There are things we have already done such as the use of triple oxide technology. This technology is optimized for reducing leakage current and maintaining high performance. Of course, there is still a lot that can be done.

Once you have the programming bit-stream you know exactly which portions of the FPGA are being used and which are not. Hence, one could switch off portions of the FPGA. But it will always be a trade-off between the power savings and the extra circuitry and cost. Today, our Spartan3L-1000 device can be programmed in hibernate mode with a leakage current that is less than six milliamps, worst case.

Silicon Strategies: Thank you.